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2cbbe090ed
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another uart demonstration: uart echo module
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2021-05-30 15:19:08 -05:00 |
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99a8661faa
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calib delay?
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2020-12-16 15:01:39 -06:00 |
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e7a23afcb0
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use 3-bit transmit state, add header/footer around data, skip debounce for now
tdc_manual_start_stop_uart_tx
tdc_uart_tx
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2020-11-02 15:49:11 -06:00 |
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45f845f671
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can transmit data out, but in wrong order ...
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2020-11-01 09:30:46 -06:00 |
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aeaf18c2d4
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skip debounce in simulation
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2020-10-30 17:52:42 -05:00 |
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ec6b3431be
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uart tx using zipcpu tut5 code
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2020-10-27 14:50:10 -05:00 |
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568775a169
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indent
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2020-10-27 10:39:56 -05:00 |
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5a58da34af
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move debouncing parts to top module
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2020-10-27 07:50:25 -05:00 |
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92f059ab54
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use only top bits of the data to display
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2020-10-26 22:45:17 -05:00 |
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124d1fff63
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add debouncing buttons before start/stop
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2020-10-26 22:33:44 -05:00 |
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c6cc9bc99f
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change divison factor in clk_gen for 100 MHz
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2020-10-26 22:00:42 -05:00 |
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61bab9153d
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hack to use PLL in synthesizing, and fake 100 MHz on verilator
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2020-10-26 21:58:13 -05:00 |
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f36bb84065
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add pin photos
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2020-10-26 18:10:42 -05:00 |
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a0b211338c
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working stop watch
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2020-10-26 17:35:52 -05:00 |
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4886fad4b2
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tdc state machine
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2020-10-26 16:06:00 -05:00 |
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74dd3fb1d8
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resume with the TDC
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2020-10-25 22:49:43 -05:00 |
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240b6e26d4
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minimal change from https://zipcpu.com/tutorial/ex-04-reqwalker.tgz
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2020-10-25 22:09:23 -05:00 |
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3a9c0343c1
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use 1 Hz clock for visible walking
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2020-10-25 21:38:28 -05:00 |
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4e192d5d70
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remove strobe parts since it is on its own branch
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2020-10-25 20:37:32 -05:00 |
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6096187250
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tut4 with busy and request
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2020-10-24 14:29:44 -05:00 |
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0a724d30d0
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make sure the verification works
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2020-10-23 19:27:49 -05:00 |
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5f18f8f88c
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formal verification stuff
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2020-10-23 19:09:57 -05:00 |
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e284e518ed
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led walker
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2020-10-23 15:50:04 -05:00 |
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66010c90d9
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assign reg in always block
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2020-10-23 15:18:09 -05:00 |
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70d8ea268e
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simulate a few more cycles
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2020-10-23 15:05:41 -05:00 |
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400ebbb9aa
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shift right as well
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2020-10-23 14:50:34 -05:00 |
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45160b50a9
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add tut3 folder, shift register code works
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2020-10-23 14:42:07 -05:00 |
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3a3830b443
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tweaks in tut 2
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2020-10-23 12:48:46 -05:00 |
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12829a3e9c
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add clock constraint, amend Makefile
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2020-10-23 11:49:21 -05:00 |
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42c5b8a47f
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timescale in verilator command
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2020-10-23 10:16:04 -05:00 |
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f9b7340667
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change width in blinky sim
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2020-10-23 09:52:03 -05:00 |
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9fe8d26364
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little improvement on Makefile
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2020-10-22 22:15:18 -05:00 |
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7bb2d41932
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create a dummy clock gen, can include it in both sim and synth
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2020-10-22 21:58:42 -05:00 |
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1198429d53
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new project for tdc, copied code from blinky and changed structure
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2020-10-22 21:28:17 -05:00 |
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ccdfe6da64
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blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet
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2020-10-19 22:25:27 -05:00 |
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08ff4b2dbb
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blinky on icefun
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2020-10-12 21:04:59 -05:00 |
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