make sure the verification works

2020-10-23 19:27:49 -05:00
parent 5f18f8f88c
commit 0a724d30d0
1 changed files with 1 additions and 0 deletions
--- a/fsm/rtl/top.v
+++ b/fsm/rtl/top.v
@@ -22,6 +22,7 @@ module top(i_clk, o_led, lcol1);
   initial begin
      obuf = 8'h1;
      {strobe, counter} = 0;
+      led_index = 0;
   end

   always @(posedge clk_12MHz)