nam/iceFun_Projects
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
3 Commits 3 Branches 2 Tags
1198429d53ee1603df1b4260bba50506cce6eb96
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Description
Projects with iceFun FPGA, written in Verilog, simulated with Verilator
backupfpgahx8kiceicefunzipcpu
266 KiB
Languages
Verilog 69.5%
Makefile 18%
C++ 12.2%
Python 0.3%