blinky on icefun
This commit is contained in:
6
.gitignore
vendored
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6
.gitignore
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*/obj_dir
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*/build
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*/*.bin
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*/*.asc
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*/*.json
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1
blinky/.gitignore
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1
blinky/.gitignore
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blinky
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45
blinky/Makefile
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45
blinky/Makefile
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SIM_TARGET = build/blinky
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BIN_TARGET = build/blinky.bin
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PCF = iceFUN.pcf
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YOSYS = yosys
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PNR = nextpnr-ice40
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IPACK = icepack
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BURN = iceFUNprog
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VERILATOR=verilator
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VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
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VINC := $(VERILATOR_ROOT)/include
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.PHONY: all burn
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all: $(SIM_TARGET) $(BIN_TARGET)
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# -GWIDTH=5 allows passing parameter to verilog module
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obj_dir/Vblinky.cpp: blinky.v
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@echo "Running verilator"
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@$(VERILATOR) --trace -Wall -GWIDTH=20 -cc blinky.v
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obj_dir/Vblinky__ALL.a: obj_dir/Vblinky.cpp
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@make --no-print-directory -C obj_dir -f Vblinky.mk
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# std=c++11 flag is needed from verilator v4.100
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$(SIM_TARGET): blinky.cpp obj_dir/Vblinky__ALL.a
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@echo "Compiling simulation executable"
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@mkdir -p build
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@g++ -I$(VINC) -I obj_dir -std=c++11 $(VINC)/verilated.cpp $(VINC)/verilated_vcd_c.cpp \
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$^ -o $@
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@echo "Run simulation with ./$(TARGET)"
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$(BIN_TARGET): blinky.v $(PCF)
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@echo "Building binary stream"
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@$(YOSYS) -p "synth_ice40 -top blinky -json build/blinky.json" -q $<
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@$(PNR) -r --hx8k --json build/blinky.json --package cb132 \
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--asc build/blinky.asc --opt-timing --pcf $(PCF) -q
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@$(IPACK) build/blinky.asc build/blinky.bin
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burn: $(BIN_TARGET)
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@$(BURN) $<
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.PHONY: clean
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clean:
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rm -rf obj_dir/ build/
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47
blinky/blinky.cpp
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47
blinky/blinky.cpp
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#include <stdio.h>
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#include <stdlib.h>
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "Vblinky.h"
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void tick(int tickcount, Vblinky *tb, VerilatedVcdC* tfp) {
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10 - 2);
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tb->i_clk = 1;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10);
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tb->i_clk = 0;
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tb->eval();
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if (tfp) {
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tfp->dump(tickcount * 10 + 5);
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tfp->flush();
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}
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}
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int main(int argc, char **argv) {
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// Call commandArgs first!
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Verilated::commandArgs(argc, argv);
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// Instantiate our design
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Vblinky *tb = new Vblinky;
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Verilated::traceEverOn(true);
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VerilatedVcdC* tfp = new VerilatedVcdC;
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tb->trace(tfp, 00);
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tfp->open("build/waveform.vcd");
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unsigned tickcount = 0;
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int last_led = tb->o_led;
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for(int k=0; k<(1 << 23); k++) {
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tick(++tickcount, tb, tfp);
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if (last_led != tb->o_led) {
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printf("k = %7d, led = %d\n", k, tb->o_led);
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}
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last_led = tb->o_led;
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}
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}
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17
blinky/blinky.v
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17
blinky/blinky.v
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`default_nettype none
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module blinky(i_clk, o_led, lcol1);
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parameter WIDTH = 24;
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input wire i_clk;
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output wire o_led;
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output wire lcol1;
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reg [WIDTH-1:0] counter;
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always @(posedge i_clk)
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counter <= counter + 1'b1;
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assign o_led = counter[WIDTH-1];
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assign lcol1 = 1'b0;
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endmodule
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5
blinky/iceFUN.pcf
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5
blinky/iceFUN.pcf
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# For iceFUN board
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set_io --warn-no-port o_led C10
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set_io --warn-no-port i_clk P7
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set_io --warn-no-port lcol1 A12
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