2020-10-12 21:04:59 -05:00
2020-10-12 21:04:59 -05:00
2020-10-12 21:04:59 -05:00
Description
Projects with iceFun FPGA, written in Verilog, simulated with Verilator
266 KiB
Languages
Verilog 69.5%
Makefile 18%
C++ 12.2%
Python 0.3%