Nam Tran 7bb2d41932 create a dummy clock gen, can include it in both sim and synth

2020-10-22 21:58:42 -05:00

blinky

blinky on icefun

2020-10-12 21:04:59 -05:00

blinky_with_pll

blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet

2020-10-19 22:25:27 -05:00

tdc

create a dummy clock gen, can include it in both sim and synth

2020-10-22 21:58:42 -05:00

.gitignore

blinky on icefun

2020-10-12 21:04:59 -05:00

Description

Projects with iceFun FPGA, written in Verilog, simulated with Verilator

backupfpgahx8kiceicefunzipcpu

266 KiB

Languages

Verilog 69.5%

Makefile 18%

C++ 12.2%

Python 0.3%