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create a dummy clock gen, can include it in both sim and synth

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Nam Tran
2020-10-22 21:58:42 -05:00
parent 1198429d53
commit 7bb2d41932
4 changed files with 41 additions and 13 deletions
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26
tdc/Makefile
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@@ -11,32 +11,36 @@ VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 |
VINC := $(VERILATOR_ROOT)/include
RTL_SRC := $(wildcard rtl/*.v)
SIM_SRC := $(wildcard sim/*.cpp)
SIM_SRC := $(wildcard sim/*.cc)
BUILD_DIR := ./build
.PHONY: all burn
all: $(SIM_TARGET) $(BIN_TARGET)
# -GWIDTH=5 allows passing parameter to verilog module
$(BUILD_DIR)/Vtop.cpp: $(RTL_SRC)
$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
@echo "Running verilator"
@mkdir -p $(BUILD_DIR)
@$(VERILATOR) --trace -Wall -GWIDTH=20 -cc $^ --top-module top --Mdir $(BUILD_DIR)
@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top --Mdir $(BUILD_DIR)
$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cpp
$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
# std=c++11 flag is needed from verilator v4.100
# std=c++11 flag is needed as of verilator v4.100
$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
@echo "Compiling simulation executable"
g++ -I$(VINC) -I$(BUILD_DIR) -std=c++11 $(VINC)/verilated.cpp\
@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
$(VINC)/verilated_vcd_c.cpp $^ -o $@
@echo "Run simulation with ./$(TARGET)"
@echo "Run simulation with ./$(SIM_TARGET)"
$(BIN_TARGET): $(RTL_SRC) $(PCF)
@echo "Building binary stream"
@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $<
@$(PNR) -r --hx8k --json build/top.json --package cb132 \
$(BUILD_DIR)/top.json: $(RTL_SRC)
@echo "Synthesizing"
@mkdir -p $(BUILD_DIR)
@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
@echo "Routing and building binary stream"
@$(PNR) -r --hx8k --json $< --package cb132 \
--asc build/top.asc --opt-timing --pcf $(PCF) -q
@$(IPACK) build/top.asc build/top.bin

13
tdc/rtl/clk_gen.v Normal file
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@@ -0,0 +1,13 @@
`default_nettype none
// dummy clock generator, should be replaced by a PLL clock gen eventually
module clk_gen(
input wire i_clk,
output wire o_clk
);
assign o_clk = i_clk;
endmodule
// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End:

13
tdc/rtl/top.v
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@@ -6,12 +6,23 @@ module top(i_clk, o_led, lcol1);
output wire o_led;
output wire lcol1;
wire clk_12MHz;
clk_gen clk_gen_0 (/*autoinst*/
// Outputs
.o_clk (clk_12MHz),
// Inputs
.i_clk (i_clk));
reg [WIDTH-1:0] counter;
always @(posedge i_clk)
always @(posedge clk_12MHz)
counter <= counter + 1'b1;
assign o_led = counter[WIDTH-1];
assign lcol1 = 1'b0;
endmodule
// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End:

2
tdc/sim/top.cpp → tdc/sim/top.cc
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@@ -35,7 +35,7 @@ int main(int argc, char **argv) {
unsigned tickcount = 0;
int last_led = tb->o_led;
for(int k=0; k<(1 << 23); k++) {
for(int k=0; k<(1 << 12); k++) {
tick(++tickcount, tb, tfp);
if (last_led != tb->o_led) {