From 7bb2d4193201cc2876bf0584f133443894f63140 Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Thu, 22 Oct 2020 21:58:42 -0500
Subject: [PATCH] create a dummy clock gen, can include it in both sim and
 synth

---
 tdc/Makefile                | 26 +++++++++++++++-----------
 tdc/rtl/clk_gen.v           | 13 +++++++++++++
 tdc/rtl/top.v               | 13 ++++++++++++-
 tdc/sim/{top.cpp => top.cc} |  2 +-
 4 files changed, 41 insertions(+), 13 deletions(-)
 create mode 100644 tdc/rtl/clk_gen.v
 rename tdc/sim/{top.cpp => top.cc} (96%)

diff --git a/tdc/Makefile b/tdc/Makefile
index 02676f8..e0cc137 100644
--- a/tdc/Makefile
+++ b/tdc/Makefile
@@ -11,32 +11,36 @@ VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 |
 VINC := $(VERILATOR_ROOT)/include
 
 RTL_SRC := $(wildcard rtl/*.v)
-SIM_SRC := $(wildcard sim/*.cpp)
+SIM_SRC := $(wildcard sim/*.cc)
 BUILD_DIR := ./build
 
 .PHONY: all burn
 all: $(SIM_TARGET)  $(BIN_TARGET)
 
 # -GWIDTH=5 allows passing parameter to verilog module
-$(BUILD_DIR)/Vtop.cpp: $(RTL_SRC)
+$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
 	@echo "Running verilator"
 	@mkdir -p $(BUILD_DIR)
-	@$(VERILATOR) --trace -Wall -GWIDTH=20 -cc $^ --top-module top --Mdir $(BUILD_DIR)
+	@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top --Mdir $(BUILD_DIR)
 
-$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cpp
+$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
 	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
 
-# std=c++11 flag is needed from verilator v4.100
+# std=c++11 flag is needed as of verilator v4.100
 $(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
 	@echo "Compiling simulation executable"
-	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++11 $(VINC)/verilated.cpp\
+	@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
 		$(VINC)/verilated_vcd_c.cpp $^ -o $@
-	@echo "Run simulation with ./$(TARGET)"
+	@echo "Run simulation with ./$(SIM_TARGET)"
 
-$(BIN_TARGET): $(RTL_SRC) $(PCF)
-	@echo "Building binary stream"
-	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $<
-	@$(PNR) -r --hx8k --json build/top.json --package cb132 \
+$(BUILD_DIR)/top.json: $(RTL_SRC)
+	@echo "Synthesizing"
+	@mkdir -p $(BUILD_DIR)
+	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
+	@echo "Routing and building binary stream"
+	@$(PNR) -r --hx8k --json $< --package cb132 \
 		--asc build/top.asc --opt-timing --pcf $(PCF) -q
 	@$(IPACK) build/top.asc build/top.bin
 
diff --git a/tdc/rtl/clk_gen.v b/tdc/rtl/clk_gen.v
new file mode 100644
index 0000000..491320f
--- /dev/null
+++ b/tdc/rtl/clk_gen.v
@@ -0,0 +1,13 @@
+`default_nettype none
+// dummy clock generator, should be replaced by a PLL clock gen eventually
+module clk_gen(
+   input wire i_clk,
+   output wire o_clk
+);
+
+assign o_clk = i_clk;
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:
diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index c0febf9..fbc8ad8 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -6,12 +6,23 @@ module top(i_clk, o_led, lcol1);
    output wire o_led;
    output wire lcol1;
 
+   wire clk_12MHz;
+
+   clk_gen clk_gen_0 (/*autoinst*/
+      // Outputs
+      .o_clk                 (clk_12MHz),
+      // Inputs
+      .i_clk                 (i_clk));
+
    reg [WIDTH-1:0] counter;
 
-   always @(posedge i_clk)
+   always @(posedge clk_12MHz)
       counter <= counter + 1'b1;
 
    assign o_led = counter[WIDTH-1];
    assign lcol1 = 1'b0;
 endmodule
 
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:
diff --git a/tdc/sim/top.cpp b/tdc/sim/top.cc
similarity index 96%
rename from tdc/sim/top.cpp
rename to tdc/sim/top.cc
index fb97897..449c98c 100644
--- a/tdc/sim/top.cpp
+++ b/tdc/sim/top.cc
@@ -35,7 +35,7 @@ int main(int argc, char **argv) {
 	unsigned tickcount = 0;
   int last_led = tb->o_led;
 
-	for(int k=0; k<(1 << 23); k++) {
+	for(int k=0; k<(1 << 12); k++) {
     tick(++tickcount, tb, tfp);
 
     if (last_led != tb->o_led) {