indent

tdc/rtl/clk_gen.v

@@ -8,7 +8,7 @@ module clk_gen #(parameter DIVISION=22)(
 
 /* verilator lint_off PINCONNECTEMPTY */
 /* verilator lint_off PINMISSING */
-   reg [DIVISION-1:0] counter = 0;
+reg [DIVISION-1:0] counter = 0;
 `ifdef VERILATOR
    always @(posedge i_clk) begin
       counter <= counter + 1;
@@ -22,7 +22,7 @@ module clk_gen #(parameter DIVISION=22)(
    end
 `endif
 
-   assign o_div_clk = counter[DIVISION-1];
+assign o_div_clk = counter[DIVISION-1];
 /* verilator lint_on PINCONNECTEMPTY */
 /* verilator lint_on PINMISSING */
 endmodule