Nam Tran 66010c90d9 assign reg in always block

2020-10-23 15:18:09 -05:00

blinky

tweaks in tut 2

2020-10-23 12:48:46 -05:00

blinky_with_pll

blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet

2020-10-19 22:25:27 -05:00

fsm

assign reg in always block

2020-10-23 15:18:09 -05:00

tdc

timescale in verilator command

2020-10-23 10:16:04 -05:00

.gitignore

add tut3 folder, shift register code works

2020-10-23 14:42:07 -05:00

Description

Projects with iceFun FPGA, written in Verilog, simulated with Verilator

backupfpgahx8kiceicefunzipcpu

266 KiB

Languages

Verilog 69.5%

Makefile 18%

C++ 12.2%

Python 0.3%