Nam Tran 42c5b8a47f timescale in verilator command

2020-10-23 10:16:04 -05:00

..

rtl

create a dummy clock gen, can include it in both sim and synth

2020-10-22 21:58:42 -05:00

sim

create a dummy clock gen, can include it in both sim and synth

2020-10-22 21:58:42 -05:00

iceFUN.pcf

new project for tdc, copied code from blinky and changed structure

2020-10-22 21:28:17 -05:00

Makefile

timescale in verilator command

2020-10-23 10:16:04 -05:00