Nam Tran c6cc9bc99f change divison factor in clk_gen for 100 MHz

2020-10-26 22:00:42 -05:00

blinky

tweaks in tut 2

2020-10-23 12:48:46 -05:00

blinky_with_pll

blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet

2020-10-19 22:25:27 -05:00

fsm

make sure the verification works

2020-10-23 19:27:49 -05:00

fsm-tut4

use 1 Hz clock for visible walking

2020-10-25 21:38:28 -05:00

tdc

change divison factor in clk_gen for 100 MHz

2020-10-26 22:00:42 -05:00

wb-tut4

minimal change from https://zipcpu.com/tutorial/ex-04-reqwalker.tgz

2020-10-25 22:09:23 -05:00

.gitignore

add tut3 folder, shift register code works

2020-10-23 14:42:07 -05:00

Description

Projects with iceFun FPGA, written in Verilog, simulated with Verilator

backupfpgahx8kiceicefunzipcpu

266 KiB

Languages

Verilog 69.5%

Makefile 18%

C++ 12.2%

Python 0.3%