minimal change from https://zipcpu.com/tutorial/ex-04-reqwalker.tgz
This commit is contained in:
68
wb-tut4/Makefile
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68
wb-tut4/Makefile
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@@ -0,0 +1,68 @@
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SIM_TARGET = build/top
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BIN_TARGET = build/top.bin
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PCF = constraints/iceFUN.pcf
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TIMING = constraints/timing.py
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YOSYS = yosys
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PNR = nextpnr-ice40
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IPACK = icepack
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BURN = iceFUNprog
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SBY = sby
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VERILATOR=verilator
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VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
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VINC := $(VERILATOR_ROOT)/include
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RTL_SRC := $(wildcard rtl/*.v)
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SIM_SRC := $(wildcard sim/*.cc)
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FV_SRC := sim/top.sby
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BUILD_DIR := ./build
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define colorecho
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@tput setaf 6
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@echo $1
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@tput sgr0
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endef
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.PHONY: all burn fv clean
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all: $(SIM_TARGET) $(BIN_TARGET)
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$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
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$(call colorecho, "Running verilator")
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mkdir -p $(BUILD_DIR)
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$(VERILATOR) --trace -Wall -cc $^ --top-module top\
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--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
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$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
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make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
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# std=c++11 flag is needed as of verilator v4.100
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$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
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$(call colorecho, "Compiling simulation executable")
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g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
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$(VINC)/verilated_vcd_c.cpp $^ -o $@
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echo "Run simulation with ./$(SIM_TARGET)"
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$(BUILD_DIR)/top.json: $(RTL_SRC)
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$(call colorecho, "Synthesizing ...")
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mkdir -p $(BUILD_DIR)
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$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
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$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
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$(call colorecho, "Routing and building binary stream ...")
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$(PNR) -r --hx8k --json $< --package cb132 \
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--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
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--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q
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$(IPACK) $(BUILD_DIR)/top.asc $@
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$(call colorecho, "Done!")
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burn: $(BIN_TARGET)
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$(BURN) $<
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fv:
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$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
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clean:
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rm -rf $(BUILD_DIR)
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$V.SILENT:
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14
wb-tut4/constraints/iceFUN.pcf
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14
wb-tut4/constraints/iceFUN.pcf
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# For iceFUN board
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set_io --warn-no-port i_clk P7
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set_io --warn-no-port i_request A5
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set_io --warn-no-port o_led_row_0 A12
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set_io --warn-no-port o_led[0] C10
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set_io --warn-no-port o_led[1] A10
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set_io --warn-no-port o_led[2] D7
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set_io --warn-no-port o_led[3] D6
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set_io --warn-no-port o_led[4] A7
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set_io --warn-no-port o_led[5] C7
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# set_io --warn-no-port o_led[6] A4
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set_io --warn-no-port o_busy C4
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1
wb-tut4/constraints/timing.py
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1
wb-tut4/constraints/timing.py
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ctx.addClock("i_clk", 100)
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13
wb-tut4/rtl/clk_gen.v
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13
wb-tut4/rtl/clk_gen.v
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`default_nettype none
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// dummy clock generator, should be replaced by a PLL clock gen eventually
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module clk_gen(
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input wire i_clk,
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output wire o_clk
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);
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assign o_clk = i_clk;
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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70
wb-tut4/rtl/top.v
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70
wb-tut4/rtl/top.v
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`default_nettype none
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module top(i_clk,
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i_cyc, i_stb, i_we, i_addr, i_data,
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o_stall, o_ack, o_data,
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o_led, o_led_row_0);
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input wire i_clk;
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//
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// Our wishbone bus interface
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input wire i_cyc, i_stb, i_we;
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input wire i_addr;
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input wire [31:0] i_data;
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//
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output wire o_stall;
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output reg o_ack;
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output wire [31:0] o_data;
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//
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// The output LED
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output wire o_led_row_0;
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output reg [5:0] o_led;
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wire busy;
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reg [3:0] state;
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initial state = 0;
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always @(posedge i_clk) begin
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if ((i_stb)&&(i_we)&&(!o_stall))
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state <= 4'h1;
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else if (state >= 4'd11)
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state <= 4'h0;
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else if (state != 0)
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state <= state + 1'b1;
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end
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always @(posedge i_clk) begin
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case(state)
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4'h1: o_led <= 6'b00_0001;
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4'h2: o_led <= 6'b00_0010;
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4'h3: o_led <= 6'b00_0100;
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4'h4: o_led <= 6'b00_1000;
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4'h5: o_led <= 6'b01_0000;
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4'h6: o_led <= 6'b10_0000;
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4'h7: o_led <= 6'b01_0000;
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4'h8: o_led <= 6'b00_1000;
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4'h9: o_led <= 6'b00_0100;
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4'ha: o_led <= 6'b00_0010;
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4'hb: o_led <= 6'b00_0001;
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default: o_led <= 6'b00_0000;
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endcase
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end
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assign busy = (state != 0);
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initial o_ack = 1'b0;
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always @(posedge i_clk)
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o_ack <= (i_stb)&&(!o_stall);
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assign o_stall = (busy)&&(i_we);
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assign o_data = { 28'h0, state };
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assign o_led_row_0 = 0;
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// Verilator lint_off UNUSED
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wire [33:0] unused;
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assign unused = { i_cyc, i_addr, i_data };
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// Verilator lint_on UNUSED
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//
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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118
wb-tut4/sim/top.cc
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118
wb-tut4/sim/top.cc
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#include <stdio.h>
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#include <stdlib.h>
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#include "Vtop.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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int tickcount = 0;
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Vtop *tb;
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VerilatedVcdC *tfp;
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void tick(void) {
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tickcount++;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10 - 2);
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tb->i_clk = 1;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10);
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tb->i_clk = 0;
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tb->eval();
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if (tfp) {
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tfp->dump(tickcount * 10 + 5);
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tfp->flush();
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}
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}
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unsigned wb_read(unsigned a) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 0;
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tb->eval();
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tb->i_addr= a;
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// Make the request
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while(tb->o_stall)
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tick();
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tick();
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tb->i_stb = 0;
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// Wait for the ACK
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while(!tb->o_ack)
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tick();
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// Idle the bus, and read the response
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tb->i_cyc = 0;
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return tb->o_data;
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}
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void wb_write(unsigned a, unsigned v) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 1;
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tb->eval();
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tb->i_addr= a;
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tb->i_data= v;
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// if busy, keep ticking
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while(tb->o_stall)
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tick();
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// Then, make the bus request
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tick();
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// and pull stb down
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tb->i_stb = 0;
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// Wait for the acknowledgement
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while(!tb->o_ack)
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tick();
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// Idle the bus and return
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tb->i_cyc = tb->i_stb = 0;
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}
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int main(int argc, char **argv) {
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int last_led, last_state = 0, state = 0;
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// Call commandArgs first!
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Verilated::commandArgs(argc, argv);
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// Instantiate our design
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tb = new Vtop;
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// Generate a trace
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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tb->trace(tfp, 99);
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tfp->open("build/waveform.vcd");
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last_led = tb->o_led;
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// Read from the current state
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printf("Initial state is: 0x%02x\n",
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wb_read(0));
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for(int cycle=0; cycle<2; cycle++) {
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// Wait five clocks
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for(int i=0; i<5; i++)
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tick();
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// Start the LEDs cycling
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wb_write(0,0);
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tick();
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while((state = wb_read(0))!=0) {
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if ((state != last_state)
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||(tb->o_led != last_led)) {
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printf("%6d: State #%2d ",
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tickcount, state);
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for(int j=0; j<6; j++) {
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if(tb->o_led & (1<<j))
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printf("O");
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else
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printf("-");
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} printf("\n");
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} tick();
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last_state = state;
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last_led = tb->o_led;
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}
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}
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tfp->close();
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delete tfp;
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delete tb;
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}
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13
wb-tut4/sim/top.sby
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13
wb-tut4/sim/top.sby
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@@ -0,0 +1,13 @@
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[options]
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mode prove
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[engines]
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smtbmc
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[script]
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read -formal *.v
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prep -top top
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[files]
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rtl/top.v
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rtl/clk_gen.v
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