another uart demonstration: uart echo module

fsm-tut4/rtl/clk_gen.v

@@ -5,7 +5,25 @@ module clk_gen(
    output wire o_clk
 );
 
-assign o_clk = i_clk;
+// assign o_clk = i_clk;
+reg [31:0] counter;
+reg buf_clk;
+parameter CLK_RATE_HZ = 12_000_000;
+
+initial  begin
+   counter = 0;
+   buf_clk = 0;
+end
+assign o_clk = buf_clk;
+
+always @(posedge i_clk) begin
+   if (counter >= CLK_RATE_HZ/2 - 1) begin
+      counter <= 0;
+      buf_clk <= ~buf_clk; 
+   end
+   else
+      counter <= counter + 1;
+end
 
 endmodule
 // Local Variables:

fsm-tut4/rtl/top.v

@@ -8,18 +8,17 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
    input wire i_request;
    output wire o_busy;
 
-   wire clk_12MHz;
+   wire clk_1Hz;
 
    clk_gen clk_gen_0 (/*autoinst*/
       // Outputs
-      .o_clk                 (clk_12MHz),
+      .o_clk                 (clk_1Hz),
       // Inputs
       .i_clk                 (i_clk));
 
    reg [WIDTH-1:0] counter;
    reg [3:0] state;
    reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED
-   // reg strobe;
    reg busy_buf;
    wire req_buf;
 
@@ -30,30 +29,26 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
 
    initial begin
       led_buf = 6'h0;
-      // {strobe, counter} = 0;
       counter = 0;
       state = 0;
       busy_buf = 0;
    end
 
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (!busy_buf && req_buf)
          busy_buf <= 1;
       else
          busy_buf <= (state != 4'h0);
    end
    // counter and strobe run only during busy signal is High
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (busy_buf)
          counter <= counter + 1'b1;
-         // {strobe, counter} <= counter + 1'b1;
       else
-         // {strobe, counter} <= 0;
          counter <= 0;
    end
 
-   // state change once strobe starts
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (!busy_buf && req_buf)
          state <= 4'h1;
       else if (state >= 4'hB)
@@ -63,62 +58,61 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
    end
 
    // fsm for led_buf
-   always @(posedge clk_12MHz) begin
-      // if (strobe)
-         case (state)
-            4'h1: led_buf <= 6'b00_0001;
-            4'h2: led_buf <= 6'b00_0010;
-            4'h3: led_buf <= 6'b00_0100;
-            4'h4: led_buf <= 6'b00_1000;
-            4'h5: led_buf <= 6'b01_0000;
-            4'h6: led_buf <= 6'b10_0000;
-            4'h7: led_buf <= 6'b01_0000;
-            4'h8: led_buf <= 6'b00_1000;
-            4'h9: led_buf <= 6'b00_0100;
-            4'ha: led_buf <= 6'b00_0010;
-            4'hb: led_buf <= 6'b00_0001;
-            default: led_buf <= 6'b00_0000;
-         endcase
-   end
-
-`ifdef	FORMAL
-   // state should never go beyond 13
-	always @(*)
-		assert(state <= 4'hd);
-
-	// I prefix all of the registers (or wires) I use in formal
-	// verification with f_, to distinguish them from the rest of the
-	// project.
-	reg	f_valid_output;
-   always @(*)
-   begin
-      // Determining if the output is valid or not is a rather
-      // complex task--unusual for a typical assertion.  Here, we'll
-      // use f_valid_output and a series of _blocking_ statements
-      // to determine if the output is one of our valid outputs.
-      f_valid_output = 0;
-
-      case(led_buf)
-         8'h01: f_valid_output = 1'b1;
-         8'h02: f_valid_output = 1'b1;
-         8'h04: f_valid_output = 1'b1;
-         8'h08: f_valid_output = 1'b1;
-         8'h10: f_valid_output = 1'b1;
-         8'h20: f_valid_output = 1'b1;
-         8'h40: f_valid_output = 1'b1;
-         8'h80: f_valid_output = 1'b1;
+   always @(posedge clk_1Hz) begin
+      case (state)
+         4'h1: led_buf <= 6'b00_0001;
+         4'h2: led_buf <= 6'b00_0010;
+         4'h3: led_buf <= 6'b00_0100;
+         4'h4: led_buf <= 6'b00_1000;
+         4'h5: led_buf <= 6'b01_0000;
+         4'h6: led_buf <= 6'b10_0000;
+         4'h7: led_buf <= 6'b01_0000;
+         4'h8: led_buf <= 6'b00_1000;
+         4'h9: led_buf <= 6'b00_0100;
+         4'ha: led_buf <= 6'b00_0010;
+         4'hb: led_buf <= 6'b00_0001;
+         default: led_buf <= 6'b00_0000;
       endcase
-
-      assert(f_valid_output);
-
-      // SV supports a $onehot function which we could've also used
-      // depending upon your version of Yosys.  This function will
-      // be true if one, and only one, bit in the argument is true.
-      // Hence we might have said
-      // assert($onehot(o_led));
-      // and avoided this case statement entirely.
    end
-`endif
+
+   `ifdef	FORMAL
+      // state should never go beyond 13
+      always @(*)
+         assert(state <= 4'hd);
+
+      // I prefix all of the registers (or wires) I use in formal
+      // verification with f_, to distinguish them from the rest of the
+      // project.
+      reg	f_valid_output;
+      always @(*)
+      begin
+         // Determining if the output is valid or not is a rather
+         // complex task--unusual for a typical assertion.  Here, we'll
+         // use f_valid_output and a series of _blocking_ statements
+         // to determine if the output is one of our valid outputs.
+         f_valid_output = 0;
+
+         case(led_buf)
+            8'h01: f_valid_output = 1'b1;
+            8'h02: f_valid_output = 1'b1;
+            8'h04: f_valid_output = 1'b1;
+            8'h08: f_valid_output = 1'b1;
+            8'h10: f_valid_output = 1'b1;
+            8'h20: f_valid_output = 1'b1;
+            8'h40: f_valid_output = 1'b1;
+            8'h80: f_valid_output = 1'b1;
+         endcase
+
+         assert(f_valid_output);
+
+         // SV supports a $onehot function which we could've also used
+         // depending upon your version of Yosys.  This function will
+         // be true if one, and only one, bit in the argument is true.
+         // Hence we might have said
+         // assert($onehot(o_led));
+         // and avoided this case statement entirely.
+      end
+   `endif
 
 endmodule
 

serialTx-tut5/Makefile

@@ -0,0 +1,72 @@
+SIM_TARGET = build/top
+BIN_TARGET = build/top.bin
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+SBY = sby
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+
+RTL_SRC := $(wildcard rtl/*.v)
+SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
+BUILD_DIR := ./build
+
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all burn fv clean sim
+all: $(SIM_TARGET)  $(BIN_TARGET)
+
+$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
+	$(call colorecho, "Running verilator")
+	mkdir -p $(BUILD_DIR)
+	$(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\
+		--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
+
+$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
+	make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+
+# std=c++11 flag is needed as of verilator v4.100
+$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
+	$(call colorecho, "Compiling simulation executable")
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
+		$(VINC)/verilated_vcd_c.cpp $^ -o $@
+	echo "Run simulation with ./$(SIM_TARGET)"
+
+$(BUILD_DIR)/top.json: $(RTL_SRC)
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+sim: $(SIM_TARGET)
+	$(call colorecho, "Running simulation")
+	$(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd
+
+burn: $(BIN_TARGET)
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+$V.SILENT:

serialTx-tut5/constraints/iceFUN.pcf

@@ -0,0 +1,8 @@
+# For iceFUN board
+
+set_io --warn-no-port i_clk  	P7
+# set_io --warn-no-port i_start_tx 	C11
+# set_io --warn-no-port i_stopN 	A11
+# set_io --warn-no-port i_resetN 	C6
+
+set_io --warn-no-port o_uart_tx A3

serialTx-tut5/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)

serialTx-tut5/rtl/clk_gen.v

@@ -0,0 +1,31 @@
+`default_nettype none
+// dummy clock generator, should be replaced by a PLL clock gen eventually
+module clk_gen #(parameter DIVISION=22)(
+   input wire i_clk,
+   output wire o_clk_100MHz,
+   output wire o_div_clk
+);
+
+/* verilator lint_off PINCONNECTEMPTY */
+/* verilator lint_off PINMISSING */
+reg [DIVISION-1:0] counter = 0;
+`ifdef VERILATOR
+   always @(posedge i_clk) begin
+      counter <= counter + 1;
+   end
+
+   assign o_clk_100MHz = i_clk;
+`else
+   pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
+   always @(posedge o_clk_100MHz) begin
+      counter <= counter + 1;
+   end
+`endif
+
+assign o_div_clk = counter[DIVISION-1];
+/* verilator lint_on PINCONNECTEMPTY */
+/* verilator lint_on PINMISSING */
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

serialTx-tut5/rtl/pll_100MHz.v

@@ -0,0 +1,40 @@
+/**
+* PLL configuration
+*
+* This Verilog module was generated automatically
+* using the icepll tool from the IceStorm project.
+* Use at your own risk.
+*
+* Given input frequency:        12.000 MHz
+* Requested output frequency:  100.000 MHz
+* Achieved output frequency:   100.500 MHz
+*/
+// this module is skipped by verilator
+`ifdef VERILATOR
+`else
+   module pll_100MHz(
+      input  i_clk,
+      output o_clk_100MHz,
+      output o_pll_locked
+   );
+
+   wire clk_int;
+   SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),		// DIVR =  0
+      .DIVF(7'b1000010),	// DIVF = 66
+      .DIVQ(3'b011),		// DIVQ =  3
+      .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+   ) uut (
+      .LOCK(o_pll_locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(i_clk),
+      .PLLOUTCORE(clk_int)
+   );
+
+   SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
+      .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
+
+endmodule
+`endif

serialTx-tut5/rtl/top.v

@@ -0,0 +1,85 @@
+`default_nettype  none
+
+module top #(parameter WIDTH=24)(
+   input wire i_clk,
+   output wire o_uart_tx
+);
+   parameter	CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
+   parameter	BAUD_RATE = 115_200; // 115.2 KBaud
+   parameter	INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
+
+   wire clk_100MHz;
+
+   /* verilator lint_off PINMISSING */
+   clk_gen #(.DIVISION(26)) clk_gen0 (.o_clk_100MHz (clk_100MHz), .i_clk (i_clk));
+   /* verilator lint_on PINMISSING */
+
+   reg tx_restart = 0;
+   reg [27:0] hz_counter;
+
+   initial hz_counter = 28'h16;
+   always @(posedge clk_100MHz) begin
+      if (hz_counter == 0)
+         hz_counter <= CLOCK_RATE_HZ - 1'b1;
+      else
+         hz_counter <= hz_counter - 1'b1;
+   end
+
+   always @(posedge clk_100MHz)
+      tx_restart <= (hz_counter == 1);
+
+   wire		tx_busy;
+   reg		tx_stb;
+   reg	[3:0]	tx_index;
+   reg	[7:0]	tx_data;
+
+   initial	tx_index = 4'h0;
+   always @(posedge clk_100MHz) begin
+      if ((tx_stb)&&(!tx_busy))
+         tx_index <= tx_index + 1'b1;
+   end
+
+   always @(posedge clk_100MHz) begin
+      case(tx_index)
+         4'h0: tx_data <= "H";
+         4'h1: tx_data <= "e";
+         4'h2: tx_data <= "l";
+         4'h3: tx_data <= "l";
+         //
+         4'h4: tx_data <= "o";
+         4'h5: tx_data <= ",";
+         4'h6: tx_data <= " ";
+         4'h7: tx_data <= "W";
+         //
+         4'h8: tx_data <= "o";
+         4'h9: tx_data <= "r";
+         4'ha: tx_data <= "l";
+         4'hb: tx_data <= "d";
+         //
+         4'hc: tx_data <= "!";
+         4'hd: tx_data <= " ";
+         4'he: tx_data <= "\n";
+         4'hf: tx_data <= "\r";
+         //
+      endcase
+   end
+
+   // tx_stb is a request to send a character.
+   initial	tx_stb = 1'b0;
+   always @(posedge clk_100MHz) begin
+      if (&tx_restart)
+         tx_stb <= 1'b1;
+      else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
+         tx_stb <= 1'b0;
+   end
+
+   //
+   // Instantiate a serial port module here
+   //
+   txuart #(INITIAL_UART_SETUP[23:0])
+   transmitter(clk_100MHz, tx_stb, tx_data, o_uart_tx, tx_busy);
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

serialTx-tut5/rtl/txuart.v

@@ -0,0 +1,267 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: 	txuart.v
+//
+// Project:	Verilog Tutorial Example file
+//
+// Purpose:	Transmit outputs over a single UART line.  This particular UART
+//		implementation has been extremely simplified: it does not handle
+//	generating break conditions, nor does it handle anything other than the
+//	8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol.
+//
+//	To interface with this module, connect it to your system clock, and
+//	pass it the byte of data you wish to transmit.  Strobe the i_wr line
+//	high for one cycle, and your data will be off.  Wait until the 'o_busy'
+//	line is low before strobing the i_wr line again--this implementation
+//	has NO BUFFER, so strobing i_wr while the core is busy will just
+//	get ignored.  The output will be placed on the o_txuart output line.
+//
+//	There are known deficiencies in the formal proof found within this
+//	module.  These have been left behind for you (the student) to fix.
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Written and distributed by Gisselquist Technology, LLC
+//
+// This program is hereby granted to the public domain.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+`default_nettype	none
+//
+//
+//
+module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
+	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
+	input	wire		i_clk;
+	input	wire		i_wr;
+	input	wire	[7:0]	i_data;
+	// And the UART output line itself
+	output	wire		o_uart_tx;
+	// A line to tell others when we are ready to accept data.  If
+	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
+	// for transmission.
+	output	reg		o_busy;
+
+	// Define several states
+	localparam [3:0] START	= 4'h0,
+		BIT_ZERO	= 4'h1,
+		BIT_ONE		= 4'h2,
+		BIT_TWO		= 4'h3,
+		BIT_THREE	= 4'h4,
+		BIT_FOUR	= 4'h5,
+		BIT_FIVE	= 4'h6,
+		BIT_SIX		= 4'h7,
+		BIT_SEVEN	= 4'h8,
+		LAST		= 4'h8,
+		IDLE		= 4'hf;
+
+	reg	[23:0]	counter;
+	reg	[3:0]	state;
+	reg	[8:0]	lcl_data;
+	reg		baud_stb;
+
+	// o_busy
+	//
+	// This is a register, designed to be true is we are ever busy above.
+	// originally, this was going to be true if we were ever not in the
+	// idle state.  The logic has since become more complex, hence we have
+	// a register dedicated to this and just copy out that registers value.
+
+	initial	o_busy = 1'b0;
+	initial	state  = IDLE;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		// Immediately start us off with a start bit
+		{ o_busy, state } <= { 1'b1, START };
+	else if (baud_stb)
+	begin
+		if (state == IDLE) // Stay in IDLE
+			{ o_busy, state } <= { 1'b0, IDLE };
+		else if (state < LAST) begin
+			o_busy <= 1'b1;
+			state <= state + 1'b1;
+		end else // Wait for IDLE
+			{ o_busy, state } <= { 1'b1, IDLE };
+	end
+
+
+
+	// lcl_data
+	//
+	// This is our working copy of the i_data register which we use
+	// when transmitting.  It is only of interest during transmit, and is
+	// allowed to be whatever at any other time.  Hence, if o_busy isn't
+	// true, we can always set it.  On the one clock where o_busy isn't
+	// true and i_wr is, we set it and o_busy is true thereafter.
+	// Then, on any baud_stb (i.e. change between baud intervals)
+	// we simple logically shift the register right to grab the next bit.
+	initial	lcl_data = 9'h1ff;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		lcl_data <= { i_data, 1'b0 };
+	else if (baud_stb)
+		lcl_data <= { 1'b1, lcl_data[8:1] };
+
+	// o_uart_tx
+	//
+	// This is the final result/output desired of this core.  It's all
+	// centered about o_uart_tx.  This is what finally needs to follow
+	// the UART protocol.
+	//
+	assign	o_uart_tx = lcl_data[0];
+
+
+	// All of the above logic is driven by the baud counter.  Bits must last
+	// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
+	// make certain of that.
+	//
+	// The basic logic is this: at the beginning of a bit interval, start
+	// the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
+	// to zero, restart it.
+	//
+	// However, comparing a 28'bit number to zero can be rather complex--
+	// especially if we wish to do anything else on that same clock.  For
+	// that reason, we create "baud_stb".  baud_stb is
+	// nothing more than a flag that is true anytime baud_counter is zero.
+	// It's true when the logic (above) needs to step to the next bit.
+	// Simple enough?
+	//
+	// I wish we could stop there, but there are some other (ugly)
+	// conditions to deal with that offer exceptions to this basic logic.
+	//
+	// 1. When the user has commanded a BREAK across the line, we need to
+	// wait several baud intervals following the break before we start
+	// transmitting, to give any receiver a chance to recognize that we are
+	// out of the break condition, and to know that the next bit will be
+	// a stop bit.
+	//
+	// 2. A reset is similar to a break condition--on both we wait several
+	// baud intervals before allowing a start bit.
+	//
+	// 3. In the idle state, we stop our counter--so that upon a request
+	// to transmit when idle we can start transmitting immediately, rather
+	// than waiting for the end of the next (fictitious and arbitrary) baud
+	// interval.
+	//
+	// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
+	// the idle state, but we also just accepted a command to start writing
+	// the next word.  At this point, the baud counter needs to be reset
+	// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
+	//
+	// The logic is a bit twisted here, in that it will only check for the
+	// above condition when baud_stb is false--so as to make
+	// certain the STOP bit is complete.
+	initial	baud_stb = 1'b1;
+	initial	counter = 0;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+	begin
+		counter  <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end else if (!baud_stb)
+	begin
+		baud_stb <= (counter == 24'h01);
+		counter  <= counter - 1'b1;
+	end else if (state != IDLE)
+	begin
+		counter <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end
+
+//
+//
+// FORMAL METHODS
+//
+//
+//
+`ifdef	FORMAL
+
+`ifdef	TXUART
+`define	ASSUME	assume
+`else
+`define	ASSUME	assert
+`endif
+
+	// Setup
+
+	reg	f_past_valid;
+
+	initial	f_past_valid = 1'b0;
+	always @(posedge i_clk)
+		f_past_valid <= 1'b1;
+
+	// Any outstanding request that was busy on the last cycle,
+	// should remain busy on this cycle
+	initial	`ASSUME(!i_wr);
+	always @(posedge i_clk)
+		if ((f_past_valid)&&($past(i_wr))&&($past(o_busy)))
+		begin
+			`ASSUME(i_wr   == $past(i_wr));
+			`ASSUME(i_data == $past(i_data));
+		end
+
+	//////////////////////////////////
+	//
+	// The contract
+	//
+	//////////////////////////////////
+
+	reg	[7:0]	fv_data;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		fv_data <= i_data;
+
+	always @(posedge i_clk)
+	case(state)
+	IDLE:		assert(o_uart_tx == 1'b1);
+	START:		assert(o_uart_tx == 1'b0);
+	BIT_ZERO:	assert(o_uart_tx == fv_data[0]);
+	BIT_ONE:	assert(o_uart_tx == fv_data[1]);
+	BIT_TWO:	assert(o_uart_tx == fv_data[2]);
+	BIT_THREE:	assert(o_uart_tx == fv_data[3]);
+	BIT_FOUR:	assert(o_uart_tx == fv_data[4]);
+	BIT_FIVE:	assert(o_uart_tx == fv_data[5]);
+	BIT_SIX:	assert(o_uart_tx == fv_data[6]);
+	BIT_SEVEN:	assert(o_uart_tx == fv_data[7]);
+	default: assert(0);
+	endcase
+
+	//////////////////////////////////
+	//
+	// Internal state checks
+	//
+	//////////////////////////////////
+
+
+	//
+	// Check the baud counter
+	//
+
+	// The baud_stb needs to be identical to our counter being zero
+	always @(posedge i_clk)
+		assert(baud_stb == (counter == 0));
+
+
+	always @(posedge i_clk)
+	if ((f_past_valid)&&($past(counter != 0)))
+		assert(counter == $past(counter - 1'b1));
+
+	always @(posedge i_clk)
+		assert(counter < CLOCKS_PER_BAUD);
+
+	always @(posedge i_clk)
+	if (!baud_stb)
+		assert(o_busy);
+
+`endif	// FORMAL
+endmodule
+

serialTx-tut5/sim/top.cc

@@ -0,0 +1,39 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include "Vtop.h"
+
+void	tick(int tickcount, Vtop *tb, VerilatedVcdC* tfp) {
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10 - 2);
+   tb->i_clk = 1;
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10);
+   tb->i_clk = 0;
+   tb->eval();
+   if (tfp) {
+      tfp->dump(tickcount * 10 + 5);
+      tfp->flush();
+   }
+}
+
+int main(int argc, char **argv) {
+   // Call commandArgs first!
+   Verilated::commandArgs(argc, argv);
+
+   // Instantiate our design
+   Vtop *tb = new Vtop;
+   Verilated::traceEverOn(true);
+   VerilatedVcdC* tfp = new VerilatedVcdC;
+
+   tb->trace(tfp, 00);
+   tfp->open("build/waveform.vcd");
+
+   unsigned tickcount = 0;
+   for (int k = 0; k < (1<<18); k++) 
+      tick(++tickcount, tb, tfp);
+
+}

tdc/Makefile

@@ -1,10 +1,12 @@
 SIM_TARGET = build/top
 BIN_TARGET = build/top.bin
-PCF = iceFUN.pcf
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
 YOSYS = yosys
 PNR = nextpnr-ice40
 IPACK = icepack
 BURN = iceFUNprog
+SBY = sby
 
 VERILATOR=verilator
 VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
@@ -12,43 +14,59 @@ VINC := $(VERILATOR_ROOT)/include
 
 RTL_SRC := $(wildcard rtl/*.v)
 SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
 BUILD_DIR := ./build
 
-.PHONY: all burn
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all burn fv clean sim
 all: $(SIM_TARGET)  $(BIN_TARGET)
 
-# -GWIDTH=5 allows passing parameter to verilog module
 $(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
-	@echo "Running verilator"
-	@mkdir -p $(BUILD_DIR)
-	@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\
+	$(call colorecho, "Running verilator")
+	mkdir -p $(BUILD_DIR)
+	$(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\
 		--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
 
 $(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
-	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+	make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
 
 # std=c++11 flag is needed as of verilator v4.100
 $(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
-	@echo "Compiling simulation executable"
-	@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
+	$(call colorecho, "Compiling simulation executable")
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
 		$(VINC)/verilated_vcd_c.cpp $^ -o $@
-	@echo "Run simulation with ./$(SIM_TARGET)"
+	echo "Run simulation with ./$(SIM_TARGET)"
 
 $(BUILD_DIR)/top.json: $(RTL_SRC)
-	@echo "Synthesizing ..."
-	@mkdir -p $(BUILD_DIR)
-	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
 
-$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
-	@echo "Routing and building binary stream ..."
-	@$(PNR) -r --hx8k --json $< --package cb132 \
-		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) -q
-	@$(IPACK) $(BUILD_DIR)/top.asc $@
-	@echo "Done!"
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+sim: $(SIM_TARGET)
+	$(call colorecho, "Running simulation")
+	$(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd
 
 burn: $(BIN_TARGET)
-	@$(BURN) $<
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
 
-.PHONY: clean
 clean:
 	rm -rf $(BUILD_DIR)
+
+$V.SILENT:

tdc/constraints/iceFUN.pcf

@@ -0,0 +1,18 @@
+# For iceFUN board
+
+set_io --warn-no-port i_clk  	P7
+set_io --warn-no-port i_startN 	C11
+set_io --warn-no-port i_stopN 	A11
+set_io --warn-no-port i_resetN 	C6
+
+set_io --warn-no-port o_led_row_0	A12
+set_io --warn-no-port o_dataN[0] 	C10
+set_io --warn-no-port o_dataN[1] 	A10
+set_io --warn-no-port o_dataN[2] 	D7
+set_io --warn-no-port o_dataN[3] 	D6
+set_io --warn-no-port o_dataN[4] 	A7
+set_io --warn-no-port o_dataN[5] 	C7
+
+set_io --warn-no-port o_ledN 	A4
+set_io --warn-no-port o_readyN 	C4
+set_io --warn-no-port o_uart_tx A3

tdc/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)

tdc/iceFUN.pcf

@@ -1,5 +0,0 @@
-# For iceFUN board
-
-set_io --warn-no-port o_led 	C10
-set_io --warn-no-port i_clk  	P7
-set_io --warn-no-port lcol1	A12

tdc/rtl/clk_gen.v

@@ -1,12 +1,30 @@
 `default_nettype none
 // dummy clock generator, should be replaced by a PLL clock gen eventually
-module clk_gen(
+module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
-   output wire o_clk
+   output wire o_clk_100MHz,
+   output wire o_div_clk
 );
 
-assign o_clk = i_clk;
+/* verilator lint_off PINCONNECTEMPTY */
+/* verilator lint_off PINMISSING */
+reg [DIVISION-1:0] counter = 0;
+`ifdef VERILATOR
+   always @(posedge i_clk) begin
+      counter <= counter + 1;
+   end
 
+   assign o_clk_100MHz = i_clk;
+`else
+   pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
+   always @(posedge o_clk_100MHz) begin
+      counter <= counter + 1;
+   end
+`endif
+
+assign o_div_clk = counter[DIVISION-1];
+/* verilator lint_on PINCONNECTEMPTY */
+/* verilator lint_on PINMISSING */
 endmodule
 // Local Variables:
 // verilog-library-directories:(".." "./rtl" ".")

tdc/rtl/debounce.v

@@ -0,0 +1,115 @@
+// Listing 5.6
+module debounce
+   (
+    input wire clk, reset,
+    input wire sw,
+    output reg db
+   );
+
+   // symbolic state declaration
+   localparam  [2:0]
+               zero    = 3'b000,
+               wait1_1 = 3'b001,
+               wait1_2 = 3'b010,
+               wait1_3 = 3'b011,
+               one     = 3'b100,
+               wait0_1 = 3'b101,
+               wait0_2 = 3'b110,
+               wait0_3 = 3'b111;
+
+   // number of counter bits (2^N * 10ns = 10ms tick)
+   localparam N =20;
+
+   // signal declaration
+   reg [N-1:0] q_reg;
+   wire [N-1:0] q_next;
+   wire m_tick;
+   reg [2:0] state_reg, state_next;
+
+   // body
+
+   //=============================================
+   // counter to generate 10 ms tick
+   //=============================================
+   always @(posedge clk)
+      q_reg <= q_next;
+   // next-state logic
+   assign q_next = q_reg + 1;
+   // output tick
+   assign m_tick = (q_reg==0) ? 1'b1 : 1'b0;
+
+   //=============================================
+   // debouncing FSM
+   //=============================================
+   // state register
+    always @(posedge clk, posedge reset)
+       if (reset)
+          state_reg <= zero;
+       else
+          state_reg <= state_next;
+
+   // next-state logic and output logic
+   always @*
+   begin
+      state_next = state_reg;  // default state: the same
+      db = 1'b0;               // default output: 0
+      case (state_reg)
+         zero:
+            if (sw)
+               state_next = wait1_1;
+         wait1_1:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = wait1_2;
+         wait1_2:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = wait1_3;
+         wait1_3:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = one;
+         one:
+            begin
+              db = 1'b1;
+              if (~sw)
+                 state_next = wait0_1;
+            end
+         wait0_1:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = wait0_2;
+            end
+         wait0_2:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = wait0_3;
+            end
+         wait0_3:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = zero;
+            end
+         default: state_next = zero;
+      endcase
+   end
+
+endmodule

tdc/rtl/pll_100MHz.v

@@ -0,0 +1,40 @@
+/**
+* PLL configuration
+*
+* This Verilog module was generated automatically
+* using the icepll tool from the IceStorm project.
+* Use at your own risk.
+*
+* Given input frequency:        12.000 MHz
+* Requested output frequency:  100.000 MHz
+* Achieved output frequency:   100.500 MHz
+*/
+// this module is skipped by verilator
+`ifdef VERILATOR
+`else
+   module pll_100MHz(
+      input  i_clk,
+      output o_clk_100MHz,
+      output o_pll_locked
+   );
+
+   wire clk_int;
+   SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),		// DIVR =  0
+      .DIVF(7'b1000010),	// DIVF = 66
+      .DIVQ(3'b011),		// DIVQ =  3
+      .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+   ) uut (
+      .LOCK(o_pll_locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(i_clk),
+      .PLLOUTCORE(clk_int)
+   );
+
+   SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
+      .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
+
+endmodule
+`endif

tdc/rtl/pos_edge_detector.v

@@ -0,0 +1,17 @@
+`default_nettype none
+module pos_edge_detector ( 
+   input wire i_sig,            // Input signal for which positive edge has to be detected
+   input wire i_clk,            // Input signal for clock
+   output wire o_pe);           // Output signal that gives a pulse when a positive edge occurs
+
+reg   sig_dly; // Internal signal to store the delayed version of signal
+
+// This always block ensures that sig_dly is exactly 1 clock behind sig
+always @ (posedge i_clk) begin
+   sig_dly <= i_sig;
+end
+
+// Combinational logic where sig is AND with delayed, inverted version of sig
+// Assign statement assigns the evaluated expression in the RHS to the internal net pe
+assign o_pe = i_sig & ~sig_dly;            
+endmodule 

tdc/rtl/tdc.v

@@ -0,0 +1,81 @@
+`default_nettype none
+
+module tdc #(parameter COUNTER_WIDTH=16)(
+   input wire i_clk,
+   input wire i_start,
+   input wire i_stop,
+   input wire i_reset,
+   output wire o_ready,
+   output wire [COUNTER_WIDTH-1:0] o_data
+);
+
+reg [COUNTER_WIDTH-1:0] counter;
+assign o_data = counter;
+
+// states
+localparam state_idle = 2'b00;
+localparam state_started = 2'b01;
+localparam state_running = 2'b10;
+localparam state_stopped = 2'b11;
+reg [1:0] current_state, next_state;
+
+// ensure that state changes each clock
+always @(posedge i_clk, posedge i_reset) begin
+   if (i_reset) begin
+      current_state <= state_idle;
+   end else begin
+      current_state <= next_state;
+   end
+end
+
+// state logic
+/* verilator lint_off COMBDLY */
+always @(*) begin
+   case (current_state)
+      state_idle: begin
+         if (i_start && (~i_stop))
+            next_state <= state_started;
+         else
+            next_state <= state_idle;
+      end
+      state_started: begin
+         if (~i_start && (~i_stop))
+            next_state <= state_running;
+         else
+            next_state <= state_started;
+      end
+      state_running: begin
+         if (~i_start && (i_stop))
+            next_state <= state_stopped;
+         else
+            next_state <= state_running;
+      end
+      state_stopped: begin
+         if (i_reset)
+            next_state <= state_idle;
+         else
+            next_state <= state_stopped;
+      end
+
+      default : next_state <= current_state;
+   endcase
+end
+/* verilator lint_on COMBDLY */
+
+// counter runs during running state only
+always @(posedge i_clk) begin
+   case (current_state)
+      state_idle: counter <= 0;
+      state_started: counter <= 0;
+      state_running: counter <= counter + 1;
+      state_stopped: counter <= counter;
+      default : counter <= 0;
+   endcase
+end
+
+assign o_ready = (current_state == state_stopped);
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

tdc/rtl/top.v

@@ -1,26 +1,131 @@
 `default_nettype  none
 
-module top(i_clk, o_led, lcol1);
-   parameter WIDTH = 24;
-   input wire i_clk;
-   output wire o_led;
-   output wire lcol1;
+/* verilator lint_off UNUSED */
+module top #(parameter WIDTH=24)(
+   input wire i_clk,
+   input wire i_startN,
+   input wire i_stopN,
+   input wire i_resetN,
+   // input wire [31:0] i_calib_delay,
+   output wire o_ledN,
+   output wire o_readyN,
+   output wire [5:0] o_dataN,
+   output wire o_led_row_0,
+   output wire o_uart_tx
+);
+   wire clk_1Hz; // 1.4 Hz actually
+   wire clk_100MHz;
+   reg buf_led = 0;
+   wire buf_ready;
+   parameter TDC_COUNTER_WIDTH = 32;
+   wire [TDC_COUNTER_WIDTH-1:0] buf_data;
+   assign o_readyN = ~buf_ready;
+   assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
 
-   wire clk_12MHz;
-
-   clk_gen clk_gen_0 (/*autoinst*/
+   /* verilator lint_off PINMISSING */
+   clk_gen #(.DIVISION(26)) clk_gen0 (
+   .o_div_clk        (clk_1Hz),
+   .o_clk_100MHz (clk_100MHz),
+   .i_clk            (i_clk));
+   /* verilator lint_on PINMISSING */
+   reg db_start, db_stop;
+   reg [31:0] cal_delay = 15000;
+   wire aa;
+   debounce db1 (
+      .db                       (aa),
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_startN ));
+   tdc_calib tcalib (
+      .o_calib_start     (db_start),
+      .o_calib_stop      (db_stop),
+      .i_clk             (i_clk),
+      // .i_delay           (i_calib_delay),
+      .i_delay           (cal_delay),
+      .i_start_btn       (aa),
+      .i_resetN          (i_resetN)
+   );
+   // always @(posedge clk_100MHz) begin
+      // db_start <= ~i_startN;
+      // db_stop <= ~i_stopN;
+   // end
+`ifdef DEBOUNCE
+   debounce db1 (
       // Outputs
-      .o_clk                 (clk_12MHz),
+      .db                       (db_start),
       // Inputs
-      .i_clk                 (i_clk));
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_startN));
+   debounce db2 (
+      // Outputs
+      .db                       (db_stop),
+      // Inputs
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_stopN));
+`endif
 
-   reg [WIDTH-1:0] counter;
+   tdc #(.COUNTER_WIDTH(32)) tdc0 (
+   // Outputs
+   .o_ready                    (buf_ready),
+   .o_data                     (buf_data),
+   // Inputs
+   .i_clk                      (clk_100MHz),
+   .i_start                    (db_start),
+   .i_stop                     (db_stop),
+   .i_reset                   (~i_resetN));
 
-   always @(posedge clk_12MHz)
-      counter <= counter + 1'b1;
+   always @(posedge clk_1Hz) begin
+      buf_led <= ~buf_led;
+   end
+
+   assign o_ledN = ~buf_led;
+   assign o_led_row_0 = 1'b0;
+
+   parameter    CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
+   parameter    BAUD_RATE = 115_200; // 115.2 KBaud
+   parameter    INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
+
+   // transferring data out every second
+   wire tx_start;
+   pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
+
+   wire         tx_busy;
+   reg          tx_stb;
+   reg  [2:0]   tx_index;
+   reg  [7:0]   tx_data;
+
+   // there are 4bytes to transmit
+   initial      tx_index = 3'd0;
+   always @(posedge clk_100MHz) begin
+      if ((tx_stb)&&(!tx_busy))
+         tx_index <= tx_index + 1'b1;
+   end
+   always @(posedge clk_100MHz) begin
+      case(tx_index)
+         3'd0: tx_data <= "f";
+         3'd1: tx_data <= "f";
+         3'd2: tx_data <= buf_data[31:24];
+         3'd3: tx_data <= buf_data[23:16];
+         3'd4: tx_data <= buf_data[15:8];
+         3'd5: tx_data <= buf_data[7:0];
+         3'd6: tx_data <= "f";
+         3'd7: tx_data <= "f";
+      endcase
+   end
+   initial      tx_stb = 1'b0;
+   // transmit only when data is ready
+   always @(posedge clk_100MHz) begin
+      if (tx_start)
+         tx_stb <= 1'b1;
+      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd7))
+         tx_stb <= 1'b0;
+   end
+
+   txuart #(INITIAL_UART_SETUP[23:0]) transmitter(clk_100MHz,
+      tx_stb, tx_data, o_uart_tx, tx_busy);
 
-   assign o_led = counter[WIDTH-1];
-   assign lcol1 = 1'b0;
 endmodule
 
 // Local Variables:

tdc/rtl/txuart.v

@@ -0,0 +1,141 @@
+`default_nettype	none
+module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
+	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
+	input	wire		i_clk;
+	input	wire		i_wr;
+	input	wire	[7:0]	i_data;
+	// And the UART output line itself
+	output	wire		o_uart_tx;
+	// A line to tell others when we are ready to accept data.  If
+	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
+	// for transmission.
+	output	reg		o_busy;
+
+	// Define several states
+	localparam [3:0] START	= 4'h0,
+		BIT_ZERO	= 4'h1,
+		BIT_ONE		= 4'h2,
+		BIT_TWO		= 4'h3,
+		BIT_THREE	= 4'h4,
+		BIT_FOUR	= 4'h5,
+		BIT_FIVE	= 4'h6,
+		BIT_SIX		= 4'h7,
+		BIT_SEVEN	= 4'h8,
+		LAST		= 4'h8,
+		IDLE		= 4'hf;
+
+	reg	[23:0]	counter;
+	reg	[3:0]	state;
+	reg	[8:0]	lcl_data;
+	reg		baud_stb;
+
+	// o_busy
+	//
+	// This is a register, designed to be true is we are ever busy above.
+	// originally, this was going to be true if we were ever not in the
+	// idle state.  The logic has since become more complex, hence we have
+	// a register dedicated to this and just copy out that registers value.
+
+	initial	o_busy = 1'b0;
+	initial	state  = IDLE;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		// Immediately start us off with a start bit
+		{ o_busy, state } <= { 1'b1, START };
+	else if (baud_stb)
+	begin
+		if (state == IDLE) // Stay in IDLE
+			{ o_busy, state } <= { 1'b0, IDLE };
+		else if (state < LAST) begin
+			o_busy <= 1'b1;
+			state <= state + 1'b1;
+		end else // Wait for IDLE
+			{ o_busy, state } <= { 1'b1, IDLE };
+	end
+
+
+
+	// lcl_data
+	//
+	// This is our working copy of the i_data register which we use
+	// when transmitting.  It is only of interest during transmit, and is
+	// allowed to be whatever at any other time.  Hence, if o_busy isn't
+	// true, we can always set it.  On the one clock where o_busy isn't
+	// true and i_wr is, we set it and o_busy is true thereafter.
+	// Then, on any baud_stb (i.e. change between baud intervals)
+	// we simple logically shift the register right to grab the next bit.
+	initial	lcl_data = 9'h1ff;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		lcl_data <= { i_data, 1'b0 };
+	else if (baud_stb)
+		lcl_data <= { 1'b1, lcl_data[8:1] };
+
+	// o_uart_tx
+	//
+	// This is the final result/output desired of this core.  It's all
+	// centered about o_uart_tx.  This is what finally needs to follow
+	// the UART protocol.
+	//
+	assign	o_uart_tx = lcl_data[0];
+
+
+	// All of the above logic is driven by the baud counter.  Bits must last
+	// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
+	// make certain of that.
+	//
+	// The basic logic is this: at the beginning of a bit interval, start
+	// the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
+	// to zero, restart it.
+	//
+	// However, comparing a 28'bit number to zero can be rather complex--
+	// especially if we wish to do anything else on that same clock.  For
+	// that reason, we create "baud_stb".  baud_stb is
+	// nothing more than a flag that is true anytime baud_counter is zero.
+	// It's true when the logic (above) needs to step to the next bit.
+	// Simple enough?
+	//
+	// I wish we could stop there, but there are some other (ugly)
+	// conditions to deal with that offer exceptions to this basic logic.
+	//
+	// 1. When the user has commanded a BREAK across the line, we need to
+	// wait several baud intervals following the break before we start
+	// transmitting, to give any receiver a chance to recognize that we are
+	// out of the break condition, and to know that the next bit will be
+	// a stop bit.
+	//
+	// 2. A reset is similar to a break condition--on both we wait several
+	// baud intervals before allowing a start bit.
+	//
+	// 3. In the idle state, we stop our counter--so that upon a request
+	// to transmit when idle we can start transmitting immediately, rather
+	// than waiting for the end of the next (fictitious and arbitrary) baud
+	// interval.
+	//
+	// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
+	// the idle state, but we also just accepted a command to start writing
+	// the next word.  At this point, the baud counter needs to be reset
+	// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
+	//
+	// The logic is a bit twisted here, in that it will only check for the
+	// above condition when baud_stb is false--so as to make
+	// certain the STOP bit is complete.
+	initial	baud_stb = 1'b1;
+	initial	counter = 0;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+	begin
+		counter  <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end else if (!baud_stb)
+	begin
+		baud_stb <= (counter == 24'h01);
+		counter  <= counter - 1'b1;
+	end else if (state != IDLE)
+	begin
+		counter <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end
+
+endmodule
+

tdc/sim/top.cc

@@ -5,43 +5,70 @@
 #include "Vtop.h"
 
 void	tick(int tickcount, Vtop *tb, VerilatedVcdC* tfp) {
-	tb->eval();
-	if (tfp)
-		tfp->dump(tickcount * 10 - 2);
-	tb->i_clk = 1;
-	tb->eval();
-	if (tfp)
-		tfp->dump(tickcount * 10);
-	tb->i_clk = 0;
-	tb->eval();
-	if (tfp) {
-		tfp->dump(tickcount * 10 + 5);
-		tfp->flush();
-	}
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10 - 2);
+   tb->i_clk = 1;
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10);
+   tb->i_clk = 0;
+   tb->eval();
+   if (tfp) {
+      tfp->dump(tickcount * 10 + 5);
+      tfp->flush();
+   }
 }
 
 int main(int argc, char **argv) {
-	// Call commandArgs first!
-	Verilated::commandArgs(argc, argv);
+   // Call commandArgs first!
+   Verilated::commandArgs(argc, argv);
 
-	// Instantiate our design
-	Vtop *tb = new Vtop;
-	Verilated::traceEverOn(true);
-	VerilatedVcdC* tfp = new VerilatedVcdC;
+   // Instantiate our design
+   Vtop *tb = new Vtop;
+   Verilated::traceEverOn(true);
+   VerilatedVcdC* tfp = new VerilatedVcdC;
 
-	tb->trace(tfp, 00);
-	tfp->open("build/waveform.vcd");
+   tb->trace(tfp, 00);
+   tfp->open("build/waveform.vcd");
 
-	unsigned tickcount = 0;
-  int last_led = tb->o_led;
+   // initial state
+   tb->i_resetN = 1;
+   tb->i_startN = 1;
+   tb->i_stopN = 1;
+   unsigned tickcount = 0;
+   for (int k = 0; k < 2; k++) 
+      tick(++tickcount, tb, tfp);
 
-	for(int k=0; k<(1 << 12); k++) {
-    tick(++tickcount, tb, tfp);
+   // reset pulse, then wait for a few clock cycles
+   tb->i_resetN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_resetN = 1;
 
-    if (last_led != tb->o_led) {
-      printf("k = %7d, led = %d\n", k, tb->o_led);
-    }
+   for (int k = 0; k < 3; k++) 
+      tick(++tickcount, tb, tfp);
 
-    last_led = tb->o_led;
-	}
+   // relevant const
+   const unsigned int main_clk_Hz = 100 * 1000 * 1000; // 100 MHz
+   const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz
+   const unsigned int db_ticks = main_clk_Hz / db_clk_Hz;
+
+   // tb->i_calib_delay = 20;
+   // start pulse
+   tb->i_startN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_startN = 1;
+
+   // for (int k = 0; k < tb->i_calib_delay + 10; k++) 
+      tick(++tickcount, tb, tfp);
+
+   for (int k = 0; k < (1<<16); k++) 
+      tick(++tickcount, tb, tfp);
+
+   tb->i_resetN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_resetN = 1;
+
+   for (int k = 0; k < 30; k++) 
+      tick(++tickcount, tb, tfp);
 }

uart/Makefile

@@ -0,0 +1,56 @@
+# Project setup
+TOP ?= top
+SIM = iverilog
+WAVE = vvp
+
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+SBY = sby
+
+BUILD_DIR = ./build
+VCD = $(BUILD_DIR)/waveform.vcd
+BIN_TARGET = build/top.bin
+
+# Files
+MODULES += $(wildcard rtl/*.v)
+TEST = tb.v
+
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all clean burn
+
+all: sim
+
+sim: $(TEST) $(MODULES)
+	@mkdir -p $(BUILD_DIR)
+	@$(SIM) -o $(BUILD_DIR)/tb_out $< $(MODULES) && $(WAVE) $(BUILD_DIR)/tb_out && open $(VCD)
+
+$(BUILD_DIR)/top.json: $(MODULES)
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top uart_echo -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+burn: $(BIN_TARGET)
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
+clean:
+	rm -rf $(BUILD_DIR)

uart/bench/uart_rx_tb.v

@@ -0,0 +1,78 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+`default_nettype none
+
+module uart_rx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire [7:0]              data_o;                 // From uut of uart_rx.v
+wire                    rx_done_o;              // From uut of uart_rx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_rx.v
+reg                     rst_n;                  // To uut of uart_rx.v
+reg                     rx_i;                   // To uut of uart_rx.v
+// End of automatics
+
+localparam clk_period = 20;
+localparam clocks_per_baud = 20;
+uart_rx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (clocks_per_baud - 1))
+        uut (/*autoinst*/
+            // Outputs
+            .data_o         (data_o[7:0]),
+            .rx_done_o      (rx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .rx_i           (rx_i));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    rx_i = 1'b1;
+end
+
+always
+    #(clk_period/2) clk = ~clk;
+
+initial begin
+    #clk_period;
+    rst_n = 0; // start reset
+    #clk_period;
+    rst_n = 1; // finish reset
+    #(clk_period * 50);
+
+    rx_i = 0; // start bit
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 0
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 1
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 2
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 3
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 4
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 5
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 6
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 7
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // stop bit
+    #(clk_period * clocks_per_baud);
+
+    #800 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_rx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/bench/uart_top_tb.v

@@ -0,0 +1,69 @@
+`timescale 1ns/100ps
+`define IVERILOG 1
+
+module uart_top_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    tx_o;                   // From uut of uart_top.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_top.v
+reg                     rst_n;                  // To uut of uart_top.v
+reg                     rx_i;                   // To uut of uart_top.v
+// End of automatics
+
+localparam T = 10; // clock cycle is 10 ticks
+localparam clocks_per_baud = 20;
+uart_echo #(/*autoinstparam*/
+              // Parameters
+              .CLOCKS_PER_BAUD             (clocks_per_baud-1))
+          uut (/*autoinst*/
+              // Outputs
+              .tx_o                     (tx_o),
+              // Inputs
+              .clk                      (clk),
+              .rst_n                    (rst_n),
+              .rx_i                     (rx_i));
+
+// setup dump and reset
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+end
+
+// clocking
+always #(T/2) clk = ~clk;
+
+// when to finish
+initial #4000 $finish; // finish at 200 ticks
+
+// other stimulus
+initial begin
+    rx_i = 1;
+    #(T) rst_n = 0;
+    #(T) rst_n = 1;
+    #(10*T);
+
+
+    rx_i = 0; // start bit
+    #(T * clocks_per_baud) rx_i = 1; // bit 0
+    #(T * clocks_per_baud) rx_i = 0; // bit 1
+    #(T * clocks_per_baud) rx_i = 1; // bit 2
+    #(T * clocks_per_baud) rx_i = 0; // bit 3
+    #(T * clocks_per_baud) rx_i = 1; // bit 4
+    #(T * clocks_per_baud) rx_i = 0; // bit 5
+    #(T * clocks_per_baud) rx_i = 1; // bit 6
+    #(T * clocks_per_baud) rx_i = 0; // bit 7
+    #(T * clocks_per_baud) rx_i = 1; // stop bit
+    #(T * clocks_per_baud);
+
+end
+endmodule // end of uart_top_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/bench/uart_tx_tb.v

@@ -0,0 +1,63 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+
+module uart_tx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    tx_done_o;              // From uut of uart_tx.v
+wire                    tx_o;                   // From uut of uart_tx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_tx.v
+reg [7:0]               data_i;                 // To uut of uart_tx.v
+reg                     en_i;                   // To uut of uart_tx.v
+reg                     rst_n;                  // To uut of uart_tx.v
+// End of automatics
+localparam CLK_PERIOD = 10;
+uart_tx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (CLK_PERIOD - 1)) uut (/*autoinst*/
+            // Outputs
+            .tx_o           (tx_o),
+            .tx_done_o      (tx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .en_i           (en_i),
+            .data_i         (data_i[7:0]));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    data_i = 0;
+end
+
+always
+    #(CLK_PERIOD/2) clk = ~clk;
+
+initial begin
+    #(CLK_PERIOD);
+
+    rst_n = 0;
+    #(CLK_PERIOD);
+    rst_n = 1;
+    #(CLK_PERIOD);
+
+    data_i = 8'h55;
+    en_i = 1;
+    #(CLK_PERIOD);
+
+    en_i = 0;
+    #(200 * CLK_PERIOD);
+
+    #400 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_tx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/constraints/iceFUN.pcf

@@ -0,0 +1,8 @@
+# For iceFUN board
+
+set_io --warn-no-port clk  	P7
+# set_io --warn-no-port i_start_tx 	C11
+set_io --warn-no-port rst_n 	C6
+
+set_io --warn-no-port tx_o A3
+set_io --warn-no-port rx_i A1

uart/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("clk", 12)

uart/rtl/uart_echo.v

@@ -0,0 +1,37 @@
+`default_nettype none
+module uart_echo #(parameter CLOCKS_PER_BAUD=16'd104)(
+           input wire clk,
+           input wire rst_n,
+           input wire rx_i,
+           output wire tx_o
+       );
+
+wire tx_en;
+wire [7:0] tx_data;
+
+uart_rx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD           (CLOCKS_PER_BAUD)) rx (/*autoinst*/
+            // Outputs
+            .data_o          (tx_data),
+            .rx_done_o       (tx_en),
+            // Inputs
+            .clk             (clk),
+            .rst_n           (rst_n),
+            .rx_i            (rx_i));
+uart_tx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD           (CLOCKS_PER_BAUD)) tx (/*autoinst*/
+            // Outputs
+            .tx_o            (tx_o),
+            .tx_done_o       (),
+            // Inputs
+            .clk             (clk),
+            .rst_n           (rst_n),
+            .en_i            (tx_en),
+            .data_i          (tx_data));
+
+endmodule
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/rtl/uart_rx.v

@@ -0,0 +1,116 @@
+`default_nettype none
+module uart_rx #(parameter CLOCKS_PER_BAUD=16'd868)(
+           input clk,
+           input rst_n,
+           input rx_i,
+           output reg [7:0] data_o,
+           output reg rx_done_o
+       );
+
+localparam clocks_per_half_bit = CLOCKS_PER_BAUD / 2;
+
+localparam s_idle = 5'b00001,
+           s_start = 5'b00010,
+           s_rd = 5'b00100,
+           s_stop = 5'b01000,
+           s_done = 5'b10000;
+
+reg en_cnt;
+reg [15:0] cnt;
+reg [4:0] state;
+reg [2:0] rx_bits;
+
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+        cnt <= 16'd0;
+    else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
+        cnt <= 16'd0;
+    else
+        cnt <= cnt + 1;
+end
+
+// edge detection
+reg rx_0, rx_1, rx_2, rx_3;
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+        rx_0 <= 0;
+        rx_1 <= 0;
+        rx_2 <= 0;
+        rx_3 <= 0;
+    end else begin
+        rx_3 <= rx_i;
+        rx_2 <= rx_3;
+        rx_1 <= rx_2;
+        rx_0 <= rx_1;
+    end
+end
+
+wire start_flag;
+assign start_flag = rx_0 & rx_1 & (~rx_2) &(~rx_3);
+
+always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
+        state <= s_idle;
+        en_cnt <= 0;
+        data_o <= 0;
+        rx_bits <= 0;
+        rx_done_o <= 0;
+    end else begin
+        case (state)
+            s_idle: begin
+                rx_bits <= 0;
+                rx_done_o <= 0;
+                if (start_flag) begin
+                    en_cnt <= 1;
+                    state <= s_start;
+                end else begin
+                    en_cnt <= 0;
+                    state <= s_idle;
+                end
+            end
+
+            s_start: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_i == 0)
+                        state <= s_rd;
+                    else
+                        state <= s_idle;
+            end
+
+            s_rd: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_bits == 3'd7)
+                        state <= s_stop;
+                    else begin
+                        data_o[rx_bits] <= rx_i;
+                        rx_bits <= rx_bits + 1;
+                        state <= s_rd;
+                    end
+            end
+
+            s_stop: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_i == 1)
+                        state <= s_done;
+                    else
+                        state <= s_idle;
+            end
+
+            s_done: begin
+                en_cnt <= 0;
+                rx_done_o <= 1;
+                state <= s_idle;
+            end
+
+            default : begin
+                state <= s_idle;
+            end
+        endcase
+    end
+end
+
+endmodule
+
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/rtl/uart_tx.v

@@ -0,0 +1,103 @@
+`default_nettype none
+module uart_tx #(parameter CLOCKS_PER_BAUD=16'd868)(
+           input wire clk,
+           input wire rst_n,
+           input wire en_i,
+           input wire [7:0] data_i,
+           output reg tx_o,
+           output reg tx_done_o
+       );
+
+localparam s_idle = 5'b00001,
+           s_start = 5'b00010,
+           s_wr = 5'b00100,
+           s_stop = 5'b01000,
+           s_done = 5'b10000;
+
+reg en_cnt;
+reg [15:0] cnt;
+reg [4:0] state;
+reg [7:0] data_r;
+reg [2:0] tx_bits;
+
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+        cnt <= 16'd0;
+    else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
+        cnt <= 16'd0;
+    else
+        cnt <= cnt + 1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
+        state <= s_idle;
+        tx_o <= 1;
+        en_cnt <= 0;
+        data_r <= 0;
+        tx_bits <= 0;
+        tx_done_o <= 0;
+    end else begin
+        case (state)
+            s_idle: begin
+                data_r <= data_i;
+                tx_bits <= 0;
+                tx_done_o <= 0;
+                if (en_i == 1) begin
+                    en_cnt <= 1;
+                    state <= s_start;
+                end else begin
+                    en_cnt <= 0;
+                    state <= s_idle;
+                end
+            end
+
+            s_start: begin
+                if (cnt == CLOCKS_PER_BAUD)
+                    state <= s_wr;
+                else begin
+                    tx_o <= 0;
+                    state <= s_start;
+                end
+            end
+
+            s_wr: begin
+                if (cnt == CLOCKS_PER_BAUD) begin
+                    if (tx_bits == 3'd7)
+                        state <= s_stop;
+                    else begin
+                        tx_bits <= tx_bits + 1;
+                        state <= s_wr;
+                    end
+                end else begin
+                    tx_o <= data_r[tx_bits];
+                    state <= s_wr;
+                end
+            end
+
+            s_stop: begin
+                if (cnt == CLOCKS_PER_BAUD)
+                    state <= s_done;
+                else begin
+                    tx_o <= 1;
+                    state <= s_stop;
+                end
+            end
+
+            s_done: begin
+                en_cnt <= 0;
+                tx_done_o <= 1;
+                state <= s_idle;
+            end
+
+            default : begin
+                state <= s_idle;
+            end
+        endcase
+    end
+end
+
+endmodule
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/tb.v

@@ -0,0 +1 @@
+bench/uart_top_tb.v

wb-tut4/Makefile

@@ -0,0 +1,68 @@
+SIM_TARGET = build/top
+BIN_TARGET = build/top.bin
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+SBY = sby
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+
+RTL_SRC := $(wildcard rtl/*.v)
+SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
+BUILD_DIR := ./build
+
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all burn fv clean
+all: $(SIM_TARGET)  $(BIN_TARGET)
+
+$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
+	$(call colorecho, "Running verilator")
+	mkdir -p $(BUILD_DIR)
+	$(VERILATOR) --trace -Wall -cc $^ --top-module top\
+		--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
+
+$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
+	make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+
+# std=c++11 flag is needed as of verilator v4.100
+$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
+	$(call colorecho, "Compiling simulation executable")
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
+		$(VINC)/verilated_vcd_c.cpp $^ -o $@
+	echo "Run simulation with ./$(SIM_TARGET)"
+
+$(BUILD_DIR)/top.json: $(RTL_SRC)
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+burn: $(BIN_TARGET)
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+$V.SILENT:

wb-tut4/constraints/iceFUN.pcf

@@ -0,0 +1,14 @@
+# For iceFUN board
+
+set_io --warn-no-port i_clk  	P7
+set_io --warn-no-port i_request 	A5
+
+set_io --warn-no-port o_led_row_0	A12
+set_io --warn-no-port o_led[0] 	C10
+set_io --warn-no-port o_led[1] 	A10
+set_io --warn-no-port o_led[2] 	D7
+set_io --warn-no-port o_led[3] 	D6
+set_io --warn-no-port o_led[4] 	A7
+set_io --warn-no-port o_led[5] 	C7
+# set_io --warn-no-port o_led[6] 	A4
+set_io --warn-no-port o_busy 	C4

wb-tut4/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)

wb-tut4/rtl/clk_gen.v

@@ -0,0 +1,13 @@
+`default_nettype none
+// dummy clock generator, should be replaced by a PLL clock gen eventually
+module clk_gen(
+   input wire i_clk,
+   output wire o_clk
+);
+
+assign o_clk = i_clk;
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

wb-tut4/rtl/top.v

@@ -0,0 +1,70 @@
+`default_nettype  none
+
+module top(i_clk,
+   i_cyc, i_stb, i_we, i_addr, i_data,
+   o_stall, o_ack, o_data,
+   o_led, o_led_row_0);
+input	wire		i_clk;
+//
+// Our wishbone bus interface
+input	wire		i_cyc, i_stb, i_we;
+input	wire		i_addr;
+input	wire	[31:0]	i_data;
+//
+output	wire		o_stall;
+output	reg		o_ack;
+output	wire	[31:0]	o_data;
+//
+// The output LED
+output wire o_led_row_0;
+output	reg	[5:0]	o_led;
+
+wire		busy;
+reg	[3:0]	state;
+
+initial	state = 0;
+always @(posedge i_clk) begin
+   if ((i_stb)&&(i_we)&&(!o_stall))
+      state <= 4'h1;
+   else if (state >= 4'd11)
+      state <= 4'h0;
+   else if (state != 0)
+      state <= state + 1'b1;
+end
+
+always @(posedge i_clk) begin
+   case(state)
+      4'h1: o_led <= 6'b00_0001;
+      4'h2: o_led <= 6'b00_0010;
+      4'h3: o_led <= 6'b00_0100;
+      4'h4: o_led <= 6'b00_1000;
+      4'h5: o_led <= 6'b01_0000;
+      4'h6: o_led <= 6'b10_0000;
+      4'h7: o_led <= 6'b01_0000;
+      4'h8: o_led <= 6'b00_1000;
+      4'h9: o_led <= 6'b00_0100;
+      4'ha: o_led <= 6'b00_0010;
+      4'hb: o_led <= 6'b00_0001;
+      default: o_led <= 6'b00_0000;
+   endcase
+end
+
+assign	busy = (state != 0);
+
+initial	o_ack = 1'b0;
+always @(posedge i_clk)
+   o_ack <= (i_stb)&&(!o_stall);
+
+assign	o_stall = (busy)&&(i_we);
+assign	o_data = { 28'h0, state };
+assign o_led_row_0 = 0;
+
+// Verilator lint_off UNUSED
+wire	[33:0]	unused;
+assign	unused = { i_cyc, i_addr, i_data };
+// Verilator lint_on  UNUSED
+//
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

wb-tut4/sim/top.cc

@@ -0,0 +1,118 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+int	tickcount = 0;
+Vtop	*tb;
+VerilatedVcdC	*tfp;
+
+void	tick(void) {
+   tickcount++;
+
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10 - 2);
+   tb->i_clk = 1;
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10);
+   tb->i_clk = 0;
+   tb->eval();
+   if (tfp) {
+      tfp->dump(tickcount * 10 + 5);
+      tfp->flush();
+   }
+}
+
+unsigned wb_read(unsigned a) {
+   tb->i_cyc = tb->i_stb = 1;
+   tb->i_we  = 0;
+   tb->eval();
+   tb->i_addr= a;
+   // Make the request
+   while(tb->o_stall)
+      tick();
+   tick();
+   tb->i_stb = 0;
+   // Wait for the ACK
+   while(!tb->o_ack)
+      tick();
+   // Idle the bus, and read the response
+   tb->i_cyc = 0;
+   return tb->o_data;
+}
+
+void wb_write(unsigned a, unsigned v) {
+   tb->i_cyc = tb->i_stb = 1;
+   tb->i_we  = 1;
+   tb->eval();
+   tb->i_addr= a;
+   tb->i_data= v;
+   // if busy, keep ticking
+   while(tb->o_stall)
+      tick();
+   // Then, make the bus request 
+   tick();
+   // and pull stb down
+   tb->i_stb = 0;
+   // Wait for the acknowledgement
+   while(!tb->o_ack)
+      tick();
+   // Idle the bus and return
+   tb->i_cyc = tb->i_stb = 0;
+}
+
+int main(int argc, char **argv) {
+   int	last_led, last_state = 0, state = 0;
+
+   // Call commandArgs first!
+   Verilated::commandArgs(argc, argv);
+
+   // Instantiate our design
+   tb = new Vtop;
+
+   // Generate a trace
+   Verilated::traceEverOn(true);
+   tfp = new VerilatedVcdC;
+   tb->trace(tfp, 99);
+   tfp->open("build/waveform.vcd");
+
+   last_led = tb->o_led;
+
+   // Read from the current state
+   printf("Initial state is: 0x%02x\n",
+         wb_read(0));
+
+   for(int cycle=0; cycle<2; cycle++) {
+      // Wait five clocks
+      for(int i=0; i<5; i++)
+         tick();
+
+      // Start the LEDs cycling
+      wb_write(0,0);
+      tick();
+
+      while((state = wb_read(0))!=0) {
+         if ((state != last_state)
+               ||(tb->o_led != last_led)) {
+            printf("%6d: State #%2d ",
+                  tickcount, state);
+            for(int j=0; j<6; j++) {
+               if(tb->o_led & (1<<j))
+                  printf("O");
+               else
+                  printf("-");
+            } printf("\n");
+         } tick();
+
+         last_state = state;
+         last_led = tb->o_led;
+      }
+   }
+
+   tfp->close();
+   delete tfp;
+   delete tb;
+}

wb-tut4/sim/top.sby

@@ -0,0 +1,13 @@
+[options]
+mode prove
+
+[engines]
+smtbmc
+
+[script]
+read -formal *.v
+prep -top top
+
+[files]
+rtl/top.v
+rtl/clk_gen.v