64 lines
1.7 KiB
Verilog
64 lines
1.7 KiB
Verilog
`timescale 1ns/1ps
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`define IVERILOG 1
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module uart_tx_tb;
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/*autowire*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire tx_done_o; // From uut of uart_tx.v
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wire tx_o; // From uut of uart_tx.v
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// End of automatics
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/*autoreginput*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg clk; // To uut of uart_tx.v
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reg [7:0] data_i; // To uut of uart_tx.v
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reg en_i; // To uut of uart_tx.v
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reg rst_n; // To uut of uart_tx.v
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// End of automatics
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localparam CLK_PERIOD = 10;
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uart_tx #(/*autoinstparam*/
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// Parameters
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.CLOCKS_PER_BAUD (CLK_PERIOD - 1)) uut (/*autoinst*/
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// Outputs
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.tx_o (tx_o),
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.tx_done_o (tx_done_o),
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// Inputs
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.clk (clk),
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.rst_n (rst_n),
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.en_i (en_i),
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.data_i (data_i[7:0]));
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initial begin
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$dumpfile("build/waveform.vcd");
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$dumpvars(0, uut);
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clk = 1'b1;
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rst_n = 1'b1;
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data_i = 0;
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end
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always
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#(CLK_PERIOD/2) clk = ~clk;
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initial begin
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#(CLK_PERIOD);
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rst_n = 0;
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#(CLK_PERIOD);
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rst_n = 1;
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#(CLK_PERIOD);
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data_i = 8'h55;
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en_i = 1;
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#(CLK_PERIOD);
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en_i = 0;
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#(200 * CLK_PERIOD);
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#400 $finish; // finish at 200 ticks
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end
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endmodule // end of uart_tx_tb
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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