79 lines
2.2 KiB
Verilog
79 lines
2.2 KiB
Verilog
`timescale 1ns/1ps
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`define IVERILOG 1
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`default_nettype none
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module uart_rx_tb;
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/*autowire*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] data_o; // From uut of uart_rx.v
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wire rx_done_o; // From uut of uart_rx.v
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// End of automatics
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/*autoreginput*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg clk; // To uut of uart_rx.v
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reg rst_n; // To uut of uart_rx.v
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reg rx_i; // To uut of uart_rx.v
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// End of automatics
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localparam clk_period = 20;
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localparam clocks_per_baud = 20;
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uart_rx #(/*autoinstparam*/
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// Parameters
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.CLOCKS_PER_BAUD (clocks_per_baud - 1))
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uut (/*autoinst*/
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// Outputs
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.data_o (data_o[7:0]),
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.rx_done_o (rx_done_o),
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// Inputs
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.clk (clk),
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.rst_n (rst_n),
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.rx_i (rx_i));
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initial begin
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$dumpfile("build/waveform.vcd");
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$dumpvars(0, uut);
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clk = 1'b1;
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rst_n = 1'b1;
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rx_i = 1'b1;
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end
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always
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#(clk_period/2) clk = ~clk;
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initial begin
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#clk_period;
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rst_n = 0; // start reset
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#clk_period;
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rst_n = 1; // finish reset
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#(clk_period * 50);
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rx_i = 0; // start bit
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#(clk_period * clocks_per_baud);
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rx_i = 1; // bit 0
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#(clk_period * clocks_per_baud);
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rx_i = 0; // bit 1
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#(clk_period * clocks_per_baud);
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rx_i = 1; // bit 2
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#(clk_period * clocks_per_baud);
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rx_i = 0; // bit 3
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#(clk_period * clocks_per_baud);
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rx_i = 1; // bit 4
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#(clk_period * clocks_per_baud);
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rx_i = 0; // bit 5
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#(clk_period * clocks_per_baud);
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rx_i = 1; // bit 6
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#(clk_period * clocks_per_baud);
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rx_i = 0; // bit 7
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#(clk_period * clocks_per_baud);
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rx_i = 1; // stop bit
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#(clk_period * clocks_per_baud);
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#800 $finish; // finish at 200 ticks
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end
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endmodule // end of uart_rx_tb
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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