38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
`default_nettype none
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module uart_echo #(parameter CLOCKS_PER_BAUD=16'd104)(
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input wire clk,
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input wire rst_n,
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input wire rx_i,
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output wire tx_o
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);
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wire tx_en;
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wire [7:0] tx_data;
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uart_rx #(/*autoinstparam*/
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// Parameters
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.CLOCKS_PER_BAUD (CLOCKS_PER_BAUD)) rx (/*autoinst*/
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// Outputs
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.data_o (tx_data),
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.rx_done_o (tx_en),
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// Inputs
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.clk (clk),
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.rst_n (rst_n),
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.rx_i (rx_i));
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uart_tx #(/*autoinstparam*/
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// Parameters
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.CLOCKS_PER_BAUD (CLOCKS_PER_BAUD)) tx (/*autoinst*/
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// Outputs
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.tx_o (tx_o),
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.tx_done_o (),
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// Inputs
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.clk (clk),
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.rst_n (rst_n),
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.en_i (tx_en),
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.data_i (tx_data));
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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