117 lines
2.7 KiB
Verilog
117 lines
2.7 KiB
Verilog
`default_nettype none
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module uart_rx #(parameter CLOCKS_PER_BAUD=16'd868)(
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input clk,
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input rst_n,
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input rx_i,
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output reg [7:0] data_o,
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output reg rx_done_o
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);
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localparam clocks_per_half_bit = CLOCKS_PER_BAUD / 2;
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localparam s_idle = 5'b00001,
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s_start = 5'b00010,
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s_rd = 5'b00100,
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s_stop = 5'b01000,
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s_done = 5'b10000;
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reg en_cnt;
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reg [15:0] cnt;
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reg [4:0] state;
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reg [2:0] rx_bits;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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cnt <= 16'd0;
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else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
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cnt <= 16'd0;
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else
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cnt <= cnt + 1;
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end
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// edge detection
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reg rx_0, rx_1, rx_2, rx_3;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rx_0 <= 0;
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rx_1 <= 0;
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rx_2 <= 0;
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rx_3 <= 0;
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end else begin
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rx_3 <= rx_i;
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rx_2 <= rx_3;
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rx_1 <= rx_2;
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rx_0 <= rx_1;
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end
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end
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wire start_flag;
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assign start_flag = rx_0 & rx_1 & (~rx_2) &(~rx_3);
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n) begin
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state <= s_idle;
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en_cnt <= 0;
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data_o <= 0;
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rx_bits <= 0;
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rx_done_o <= 0;
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end else begin
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case (state)
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s_idle: begin
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rx_bits <= 0;
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rx_done_o <= 0;
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if (start_flag) begin
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en_cnt <= 1;
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state <= s_start;
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end else begin
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en_cnt <= 0;
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state <= s_idle;
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end
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end
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s_start: begin
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if (cnt == clocks_per_half_bit)
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if (rx_i == 0)
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state <= s_rd;
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else
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state <= s_idle;
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end
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s_rd: begin
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if (cnt == clocks_per_half_bit)
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if (rx_bits == 3'd7)
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state <= s_stop;
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else begin
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data_o[rx_bits] <= rx_i;
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rx_bits <= rx_bits + 1;
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state <= s_rd;
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end
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end
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s_stop: begin
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if (cnt == clocks_per_half_bit)
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if (rx_i == 1)
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state <= s_done;
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else
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state <= s_idle;
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end
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s_done: begin
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en_cnt <= 0;
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rx_done_o <= 1;
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state <= s_idle;
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end
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default : begin
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state <= s_idle;
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end
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endcase
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end
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end
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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