70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
`timescale 1ns/100ps
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`define IVERILOG 1
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module uart_top_tb;
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/*autowire*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire tx_o; // From uut of uart_top.v
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// End of automatics
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/*autoreginput*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg clk; // To uut of uart_top.v
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reg rst_n; // To uut of uart_top.v
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reg rx_i; // To uut of uart_top.v
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// End of automatics
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localparam T = 10; // clock cycle is 10 ticks
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localparam clocks_per_baud = 20;
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uart_echo #(/*autoinstparam*/
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// Parameters
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.CLOCKS_PER_BAUD (clocks_per_baud-1))
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uut (/*autoinst*/
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// Outputs
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.tx_o (tx_o),
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// Inputs
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.clk (clk),
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.rst_n (rst_n),
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.rx_i (rx_i));
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// setup dump and reset
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initial begin
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$dumpfile("build/waveform.vcd");
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$dumpvars(0, uut);
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clk = 1'b1;
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rst_n = 1'b1;
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end
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// clocking
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always #(T/2) clk = ~clk;
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// when to finish
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initial #4000 $finish; // finish at 200 ticks
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// other stimulus
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initial begin
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rx_i = 1;
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#(T) rst_n = 0;
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#(T) rst_n = 1;
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#(10*T);
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rx_i = 0; // start bit
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#(T * clocks_per_baud) rx_i = 1; // bit 0
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#(T * clocks_per_baud) rx_i = 0; // bit 1
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#(T * clocks_per_baud) rx_i = 1; // bit 2
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#(T * clocks_per_baud) rx_i = 0; // bit 3
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#(T * clocks_per_baud) rx_i = 1; // bit 4
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#(T * clocks_per_baud) rx_i = 0; // bit 5
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#(T * clocks_per_baud) rx_i = 1; // bit 6
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#(T * clocks_per_baud) rx_i = 0; // bit 7
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#(T * clocks_per_baud) rx_i = 1; // stop bit
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#(T * clocks_per_baud);
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end
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endmodule // end of uart_top_tb
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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