`timescale 1ns/100ps
`define IVERILOG 1

module uart_top_tb;
/*autowire*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    tx_o;                   // From uut of uart_top.v
// End of automatics
/*autoreginput*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg                     clk;                    // To uut of uart_top.v
reg                     rst_n;                  // To uut of uart_top.v
reg                     rx_i;                   // To uut of uart_top.v
// End of automatics

localparam T = 10; // clock cycle is 10 ticks
localparam clocks_per_baud = 20;
uart_echo #(/*autoinstparam*/
              // Parameters
              .CLOCKS_PER_BAUD             (clocks_per_baud-1))
          uut (/*autoinst*/
              // Outputs
              .tx_o                     (tx_o),
              // Inputs
              .clk                      (clk),
              .rst_n                    (rst_n),
              .rx_i                     (rx_i));

// setup dump and reset
initial begin
    $dumpfile("build/waveform.vcd");
    $dumpvars(0, uut);

    clk = 1'b1;
    rst_n = 1'b1;
end

// clocking
always #(T/2) clk = ~clk;

// when to finish
initial #4000 $finish; // finish at 200 ticks

// other stimulus
initial begin
    rx_i = 1;
    #(T) rst_n = 0;
    #(T) rst_n = 1;
    #(10*T);


    rx_i = 0; // start bit
    #(T * clocks_per_baud) rx_i = 1; // bit 0
    #(T * clocks_per_baud) rx_i = 0; // bit 1
    #(T * clocks_per_baud) rx_i = 1; // bit 2
    #(T * clocks_per_baud) rx_i = 0; // bit 3
    #(T * clocks_per_baud) rx_i = 1; // bit 4
    #(T * clocks_per_baud) rx_i = 0; // bit 5
    #(T * clocks_per_baud) rx_i = 1; // bit 6
    #(T * clocks_per_baud) rx_i = 0; // bit 7
    #(T * clocks_per_baud) rx_i = 1; // stop bit
    #(T * clocks_per_baud);

end
endmodule // end of uart_top_tb

          // Local Variables:
          // verilog-library-directories:(".." "../rtl" ".")
          // End: