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70d8ea268e
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simulate a few more cycles
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2020-10-23 15:05:41 -05:00 |
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400ebbb9aa
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shift right as well
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2020-10-23 14:50:34 -05:00 |
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45160b50a9
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add tut3 folder, shift register code works
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2020-10-23 14:42:07 -05:00 |
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3a3830b443
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tweaks in tut 2
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2020-10-23 12:48:46 -05:00 |
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12829a3e9c
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add clock constraint, amend Makefile
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2020-10-23 11:49:21 -05:00 |
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42c5b8a47f
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timescale in verilator command
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2020-10-23 10:16:04 -05:00 |
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f9b7340667
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change width in blinky sim
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2020-10-23 09:52:03 -05:00 |
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9fe8d26364
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little improvement on Makefile
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2020-10-22 22:15:18 -05:00 |
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7bb2d41932
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create a dummy clock gen, can include it in both sim and synth
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2020-10-22 21:58:42 -05:00 |
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1198429d53
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new project for tdc, copied code from blinky and changed structure
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2020-10-22 21:28:17 -05:00 |
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ccdfe6da64
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blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet
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2020-10-19 22:25:27 -05:00 |
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08ff4b2dbb
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blinky on icefun
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2020-10-12 21:04:59 -05:00 |
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