another uart demonstration: uart echo module

tdc/constraints/iceFUN.pcf

@@ -15,3 +15,4 @@ set_io --warn-no-port o_dataN[5] 	C7
 
 set_io --warn-no-port o_ledN 	A4
 set_io --warn-no-port o_readyN 	C4
+set_io --warn-no-port o_uart_tx A3

tdc/rtl/pos_edge_detector.v

@@ -0,0 +1,17 @@
+`default_nettype none
+module pos_edge_detector ( 
+   input wire i_sig,            // Input signal for which positive edge has to be detected
+   input wire i_clk,            // Input signal for clock
+   output wire o_pe);           // Output signal that gives a pulse when a positive edge occurs
+
+reg   sig_dly; // Internal signal to store the delayed version of signal
+
+// This always block ensures that sig_dly is exactly 1 clock behind sig
+always @ (posedge i_clk) begin
+   sig_dly <= i_sig;
+end
+
+// Combinational logic where sig is AND with delayed, inverted version of sig
+// Assign statement assigns the evaluated expression in the RHS to the internal net pe
+assign o_pe = i_sig & ~sig_dly;            
+endmodule 

tdc/rtl/top.v

@@ -1,50 +1,72 @@
 `default_nettype  none
 
+/* verilator lint_off UNUSED */
 module top #(parameter WIDTH=24)(
    input wire i_clk,
    input wire i_startN,
    input wire i_stopN,
    input wire i_resetN,
+   // input wire [31:0] i_calib_delay,
    output wire o_ledN,
    output wire o_readyN,
    output wire [5:0] o_dataN,
-   output wire o_led_row_0
+   output wire o_led_row_0,
+   output wire o_uart_tx
 );
    wire clk_1Hz; // 1.4 Hz actually
    wire clk_100MHz;
    reg buf_led = 0;
    wire buf_ready;
-   /* verilator lint_off UNUSED */
+   parameter TDC_COUNTER_WIDTH = 32;
-   parameter TDC_COUNTER_WIDTH = 28;
    wire [TDC_COUNTER_WIDTH-1:0] buf_data;
    assign o_readyN = ~buf_ready;
    assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
-   /* verilator lint_on UNUSED */
 
-/* verilator lint_off PINMISSING */
+   /* verilator lint_off PINMISSING */
    clk_gen #(.DIVISION(26)) clk_gen0 (
    .o_div_clk        (clk_1Hz),
    .o_clk_100MHz (clk_100MHz),
    .i_clk            (i_clk));
-/* verilator lint_on PINMISSING */
+   /* verilator lint_on PINMISSING */
-
+   reg db_start, db_stop;
-reg db_start, db_stop;
+   reg [31:0] cal_delay = 15000;
-debounce db1 (
+   wire aa;
+   debounce db1 (
+      .db                       (aa),
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_startN ));
+   tdc_calib tcalib (
+      .o_calib_start     (db_start),
+      .o_calib_stop      (db_stop),
+      .i_clk             (i_clk),
+      // .i_delay           (i_calib_delay),
+      .i_delay           (cal_delay),
+      .i_start_btn       (aa),
+      .i_resetN          (i_resetN)
+   );
+   // always @(posedge clk_100MHz) begin
+      // db_start <= ~i_startN;
+      // db_stop <= ~i_stopN;
+   // end
+`ifdef DEBOUNCE
+   debounce db1 (
       // Outputs
       .db                       (db_start),
       // Inputs
       .clk                      (clk_100MHz),
       .reset                    (~i_resetN),
       .sw                       (~i_startN));
-debounce db2 (
+   debounce db2 (
       // Outputs
       .db                       (db_stop),
       // Inputs
       .clk                      (clk_100MHz),
       .reset                    (~i_resetN),
       .sw                       (~i_stopN));
+`endif
 
-   tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
+   tdc #(.COUNTER_WIDTH(32)) tdc0 (
    // Outputs
    .o_ready                    (buf_ready),
    .o_data                     (buf_data),
@@ -60,6 +82,50 @@ debounce db2 (
 
    assign o_ledN = ~buf_led;
    assign o_led_row_0 = 1'b0;
+
+   parameter    CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
+   parameter    BAUD_RATE = 115_200; // 115.2 KBaud
+   parameter    INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
+
+   // transferring data out every second
+   wire tx_start;
+   pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
+
+   wire         tx_busy;
+   reg          tx_stb;
+   reg  [2:0]   tx_index;
+   reg  [7:0]   tx_data;
+
+   // there are 4bytes to transmit
+   initial      tx_index = 3'd0;
+   always @(posedge clk_100MHz) begin
+      if ((tx_stb)&&(!tx_busy))
+         tx_index <= tx_index + 1'b1;
+   end
+   always @(posedge clk_100MHz) begin
+      case(tx_index)
+         3'd0: tx_data <= "f";
+         3'd1: tx_data <= "f";
+         3'd2: tx_data <= buf_data[31:24];
+         3'd3: tx_data <= buf_data[23:16];
+         3'd4: tx_data <= buf_data[15:8];
+         3'd5: tx_data <= buf_data[7:0];
+         3'd6: tx_data <= "f";
+         3'd7: tx_data <= "f";
+      endcase
+   end
+   initial      tx_stb = 1'b0;
+   // transmit only when data is ready
+   always @(posedge clk_100MHz) begin
+      if (tx_start)
+         tx_stb <= 1'b1;
+      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd7))
+         tx_stb <= 1'b0;
+   end
+
+   txuart #(INITIAL_UART_SETUP[23:0]) transmitter(clk_100MHz,
+      tx_stb, tx_data, o_uart_tx, tx_busy);
+
 endmodule
 
 // Local Variables:

tdc/rtl/txuart.v

@@ -0,0 +1,141 @@
+`default_nettype	none
+module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
+	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
+	input	wire		i_clk;
+	input	wire		i_wr;
+	input	wire	[7:0]	i_data;
+	// And the UART output line itself
+	output	wire		o_uart_tx;
+	// A line to tell others when we are ready to accept data.  If
+	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
+	// for transmission.
+	output	reg		o_busy;
+
+	// Define several states
+	localparam [3:0] START	= 4'h0,
+		BIT_ZERO	= 4'h1,
+		BIT_ONE		= 4'h2,
+		BIT_TWO		= 4'h3,
+		BIT_THREE	= 4'h4,
+		BIT_FOUR	= 4'h5,
+		BIT_FIVE	= 4'h6,
+		BIT_SIX		= 4'h7,
+		BIT_SEVEN	= 4'h8,
+		LAST		= 4'h8,
+		IDLE		= 4'hf;
+
+	reg	[23:0]	counter;
+	reg	[3:0]	state;
+	reg	[8:0]	lcl_data;
+	reg		baud_stb;
+
+	// o_busy
+	//
+	// This is a register, designed to be true is we are ever busy above.
+	// originally, this was going to be true if we were ever not in the
+	// idle state.  The logic has since become more complex, hence we have
+	// a register dedicated to this and just copy out that registers value.
+
+	initial	o_busy = 1'b0;
+	initial	state  = IDLE;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		// Immediately start us off with a start bit
+		{ o_busy, state } <= { 1'b1, START };
+	else if (baud_stb)
+	begin
+		if (state == IDLE) // Stay in IDLE
+			{ o_busy, state } <= { 1'b0, IDLE };
+		else if (state < LAST) begin
+			o_busy <= 1'b1;
+			state <= state + 1'b1;
+		end else // Wait for IDLE
+			{ o_busy, state } <= { 1'b1, IDLE };
+	end
+
+
+
+	// lcl_data
+	//
+	// This is our working copy of the i_data register which we use
+	// when transmitting.  It is only of interest during transmit, and is
+	// allowed to be whatever at any other time.  Hence, if o_busy isn't
+	// true, we can always set it.  On the one clock where o_busy isn't
+	// true and i_wr is, we set it and o_busy is true thereafter.
+	// Then, on any baud_stb (i.e. change between baud intervals)
+	// we simple logically shift the register right to grab the next bit.
+	initial	lcl_data = 9'h1ff;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		lcl_data <= { i_data, 1'b0 };
+	else if (baud_stb)
+		lcl_data <= { 1'b1, lcl_data[8:1] };
+
+	// o_uart_tx
+	//
+	// This is the final result/output desired of this core.  It's all
+	// centered about o_uart_tx.  This is what finally needs to follow
+	// the UART protocol.
+	//
+	assign	o_uart_tx = lcl_data[0];
+
+
+	// All of the above logic is driven by the baud counter.  Bits must last
+	// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
+	// make certain of that.
+	//
+	// The basic logic is this: at the beginning of a bit interval, start
+	// the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
+	// to zero, restart it.
+	//
+	// However, comparing a 28'bit number to zero can be rather complex--
+	// especially if we wish to do anything else on that same clock.  For
+	// that reason, we create "baud_stb".  baud_stb is
+	// nothing more than a flag that is true anytime baud_counter is zero.
+	// It's true when the logic (above) needs to step to the next bit.
+	// Simple enough?
+	//
+	// I wish we could stop there, but there are some other (ugly)
+	// conditions to deal with that offer exceptions to this basic logic.
+	//
+	// 1. When the user has commanded a BREAK across the line, we need to
+	// wait several baud intervals following the break before we start
+	// transmitting, to give any receiver a chance to recognize that we are
+	// out of the break condition, and to know that the next bit will be
+	// a stop bit.
+	//
+	// 2. A reset is similar to a break condition--on both we wait several
+	// baud intervals before allowing a start bit.
+	//
+	// 3. In the idle state, we stop our counter--so that upon a request
+	// to transmit when idle we can start transmitting immediately, rather
+	// than waiting for the end of the next (fictitious and arbitrary) baud
+	// interval.
+	//
+	// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
+	// the idle state, but we also just accepted a command to start writing
+	// the next word.  At this point, the baud counter needs to be reset
+	// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
+	//
+	// The logic is a bit twisted here, in that it will only check for the
+	// above condition when baud_stb is false--so as to make
+	// certain the STOP bit is complete.
+	initial	baud_stb = 1'b1;
+	initial	counter = 0;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+	begin
+		counter  <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end else if (!baud_stb)
+	begin
+		baud_stb <= (counter == 24'h01);
+		counter  <= counter - 1'b1;
+	end else if (state != IDLE)
+	begin
+		counter <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end
+
+endmodule
+

tdc/sim/top.cc

@@ -32,6 +32,7 @@ int main(int argc, char **argv) {
    tb->trace(tfp, 00);
    tfp->open("build/waveform.vcd");
 
+   // initial state
    tb->i_resetN = 1;
    tb->i_startN = 1;
    tb->i_stopN = 1;
@@ -39,6 +40,7 @@ int main(int argc, char **argv) {
    for (int k = 0; k < 2; k++) 
       tick(++tickcount, tb, tfp);
 
+   // reset pulse, then wait for a few clock cycles
    tb->i_resetN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_resetN = 1;
@@ -46,27 +48,27 @@ int main(int argc, char **argv) {
    for (int k = 0; k < 3; k++) 
       tick(++tickcount, tb, tfp);
 
-   for (int i = 0; i < 1000; i++) {
+   // relevant const
+   const unsigned int main_clk_Hz = 100 * 1000 * 1000; // 100 MHz
+   const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz
+   const unsigned int db_ticks = main_clk_Hz / db_clk_Hz;
+
+   // tb->i_calib_delay = 20;
+   // start pulse
    tb->i_startN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_startN = 1;
-      tick(++tickcount, tb, tfp);
-   }
 
-   for (int k = 0; k < 15; k++) 
+   // for (int k = 0; k < tb->i_calib_delay + 10; k++) 
       tick(++tickcount, tb, tfp);
 
-   tb->i_stopN = 0;
+   for (int k = 0; k < (1<<16); k++) 
-   tick(++tickcount, tb, tfp);
-   tb->i_stopN = 1;
-
-   for (int k = 0; k < 3; k++) 
       tick(++tickcount, tb, tfp);
 
    tb->i_resetN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_resetN = 1;
 
-   for (int k = 0; k < 3; k++) 
+   for (int k = 0; k < 30; k++) 
       tick(++tickcount, tb, tfp);
 }

uart/Makefile

@@ -0,0 +1,56 @@
+# Project setup
+TOP ?= top
+SIM = iverilog
+WAVE = vvp
+
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+SBY = sby
+
+BUILD_DIR = ./build
+VCD = $(BUILD_DIR)/waveform.vcd
+BIN_TARGET = build/top.bin
+
+# Files
+MODULES += $(wildcard rtl/*.v)
+TEST = tb.v
+
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all clean burn
+
+all: sim
+
+sim: $(TEST) $(MODULES)
+	@mkdir -p $(BUILD_DIR)
+	@$(SIM) -o $(BUILD_DIR)/tb_out $< $(MODULES) && $(WAVE) $(BUILD_DIR)/tb_out && open $(VCD)
+
+$(BUILD_DIR)/top.json: $(MODULES)
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top uart_echo -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+burn: $(BIN_TARGET)
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
+clean:
+	rm -rf $(BUILD_DIR)

uart/bench/uart_rx_tb.v

@@ -0,0 +1,78 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+`default_nettype none
+
+module uart_rx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire [7:0]              data_o;                 // From uut of uart_rx.v
+wire                    rx_done_o;              // From uut of uart_rx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_rx.v
+reg                     rst_n;                  // To uut of uart_rx.v
+reg                     rx_i;                   // To uut of uart_rx.v
+// End of automatics
+
+localparam clk_period = 20;
+localparam clocks_per_baud = 20;
+uart_rx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (clocks_per_baud - 1))
+        uut (/*autoinst*/
+            // Outputs
+            .data_o         (data_o[7:0]),
+            .rx_done_o      (rx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .rx_i           (rx_i));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    rx_i = 1'b1;
+end
+
+always
+    #(clk_period/2) clk = ~clk;
+
+initial begin
+    #clk_period;
+    rst_n = 0; // start reset
+    #clk_period;
+    rst_n = 1; // finish reset
+    #(clk_period * 50);
+
+    rx_i = 0; // start bit
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 0
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 1
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 2
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 3
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 4
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 5
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 6
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 7
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // stop bit
+    #(clk_period * clocks_per_baud);
+
+    #800 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_rx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/bench/uart_top_tb.v

@@ -0,0 +1,69 @@
+`timescale 1ns/100ps
+`define IVERILOG 1
+
+module uart_top_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    tx_o;                   // From uut of uart_top.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_top.v
+reg                     rst_n;                  // To uut of uart_top.v
+reg                     rx_i;                   // To uut of uart_top.v
+// End of automatics
+
+localparam T = 10; // clock cycle is 10 ticks
+localparam clocks_per_baud = 20;
+uart_echo #(/*autoinstparam*/
+              // Parameters
+              .CLOCKS_PER_BAUD             (clocks_per_baud-1))
+          uut (/*autoinst*/
+              // Outputs
+              .tx_o                     (tx_o),
+              // Inputs
+              .clk                      (clk),
+              .rst_n                    (rst_n),
+              .rx_i                     (rx_i));
+
+// setup dump and reset
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+end
+
+// clocking
+always #(T/2) clk = ~clk;
+
+// when to finish
+initial #4000 $finish; // finish at 200 ticks
+
+// other stimulus
+initial begin
+    rx_i = 1;
+    #(T) rst_n = 0;
+    #(T) rst_n = 1;
+    #(10*T);
+
+
+    rx_i = 0; // start bit
+    #(T * clocks_per_baud) rx_i = 1; // bit 0
+    #(T * clocks_per_baud) rx_i = 0; // bit 1
+    #(T * clocks_per_baud) rx_i = 1; // bit 2
+    #(T * clocks_per_baud) rx_i = 0; // bit 3
+    #(T * clocks_per_baud) rx_i = 1; // bit 4
+    #(T * clocks_per_baud) rx_i = 0; // bit 5
+    #(T * clocks_per_baud) rx_i = 1; // bit 6
+    #(T * clocks_per_baud) rx_i = 0; // bit 7
+    #(T * clocks_per_baud) rx_i = 1; // stop bit
+    #(T * clocks_per_baud);
+
+end
+endmodule // end of uart_top_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/bench/uart_tx_tb.v

@@ -0,0 +1,63 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+
+module uart_tx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    tx_done_o;              // From uut of uart_tx.v
+wire                    tx_o;                   // From uut of uart_tx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_tx.v
+reg [7:0]               data_i;                 // To uut of uart_tx.v
+reg                     en_i;                   // To uut of uart_tx.v
+reg                     rst_n;                  // To uut of uart_tx.v
+// End of automatics
+localparam CLK_PERIOD = 10;
+uart_tx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (CLK_PERIOD - 1)) uut (/*autoinst*/
+            // Outputs
+            .tx_o           (tx_o),
+            .tx_done_o      (tx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .en_i           (en_i),
+            .data_i         (data_i[7:0]));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    data_i = 0;
+end
+
+always
+    #(CLK_PERIOD/2) clk = ~clk;
+
+initial begin
+    #(CLK_PERIOD);
+
+    rst_n = 0;
+    #(CLK_PERIOD);
+    rst_n = 1;
+    #(CLK_PERIOD);
+
+    data_i = 8'h55;
+    en_i = 1;
+    #(CLK_PERIOD);
+
+    en_i = 0;
+    #(200 * CLK_PERIOD);
+
+    #400 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_tx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End:

uart/constraints/iceFUN.pcf

@@ -0,0 +1,8 @@
+# For iceFUN board
+
+set_io --warn-no-port clk  	P7
+# set_io --warn-no-port i_start_tx 	C11
+set_io --warn-no-port rst_n 	C6
+
+set_io --warn-no-port tx_o A3
+set_io --warn-no-port rx_i A1

uart/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("clk", 12)

uart/rtl/uart_echo.v

@@ -0,0 +1,37 @@
+`default_nettype none
+module uart_echo #(parameter CLOCKS_PER_BAUD=16'd104)(
+           input wire clk,
+           input wire rst_n,
+           input wire rx_i,
+           output wire tx_o
+       );
+
+wire tx_en;
+wire [7:0] tx_data;
+
+uart_rx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD           (CLOCKS_PER_BAUD)) rx (/*autoinst*/
+            // Outputs
+            .data_o          (tx_data),
+            .rx_done_o       (tx_en),
+            // Inputs
+            .clk             (clk),
+            .rst_n           (rst_n),
+            .rx_i            (rx_i));
+uart_tx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD           (CLOCKS_PER_BAUD)) tx (/*autoinst*/
+            // Outputs
+            .tx_o            (tx_o),
+            .tx_done_o       (),
+            // Inputs
+            .clk             (clk),
+            .rst_n           (rst_n),
+            .en_i            (tx_en),
+            .data_i          (tx_data));
+
+endmodule
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/rtl/uart_rx.v

@@ -0,0 +1,116 @@
+`default_nettype none
+module uart_rx #(parameter CLOCKS_PER_BAUD=16'd868)(
+           input clk,
+           input rst_n,
+           input rx_i,
+           output reg [7:0] data_o,
+           output reg rx_done_o
+       );
+
+localparam clocks_per_half_bit = CLOCKS_PER_BAUD / 2;
+
+localparam s_idle = 5'b00001,
+           s_start = 5'b00010,
+           s_rd = 5'b00100,
+           s_stop = 5'b01000,
+           s_done = 5'b10000;
+
+reg en_cnt;
+reg [15:0] cnt;
+reg [4:0] state;
+reg [2:0] rx_bits;
+
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+        cnt <= 16'd0;
+    else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
+        cnt <= 16'd0;
+    else
+        cnt <= cnt + 1;
+end
+
+// edge detection
+reg rx_0, rx_1, rx_2, rx_3;
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+        rx_0 <= 0;
+        rx_1 <= 0;
+        rx_2 <= 0;
+        rx_3 <= 0;
+    end else begin
+        rx_3 <= rx_i;
+        rx_2 <= rx_3;
+        rx_1 <= rx_2;
+        rx_0 <= rx_1;
+    end
+end
+
+wire start_flag;
+assign start_flag = rx_0 & rx_1 & (~rx_2) &(~rx_3);
+
+always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
+        state <= s_idle;
+        en_cnt <= 0;
+        data_o <= 0;
+        rx_bits <= 0;
+        rx_done_o <= 0;
+    end else begin
+        case (state)
+            s_idle: begin
+                rx_bits <= 0;
+                rx_done_o <= 0;
+                if (start_flag) begin
+                    en_cnt <= 1;
+                    state <= s_start;
+                end else begin
+                    en_cnt <= 0;
+                    state <= s_idle;
+                end
+            end
+
+            s_start: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_i == 0)
+                        state <= s_rd;
+                    else
+                        state <= s_idle;
+            end
+
+            s_rd: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_bits == 3'd7)
+                        state <= s_stop;
+                    else begin
+                        data_o[rx_bits] <= rx_i;
+                        rx_bits <= rx_bits + 1;
+                        state <= s_rd;
+                    end
+            end
+
+            s_stop: begin
+                if (cnt == clocks_per_half_bit)
+                    if (rx_i == 1)
+                        state <= s_done;
+                    else
+                        state <= s_idle;
+            end
+
+            s_done: begin
+                en_cnt <= 0;
+                rx_done_o <= 1;
+                state <= s_idle;
+            end
+
+            default : begin
+                state <= s_idle;
+            end
+        endcase
+    end
+end
+
+endmodule
+
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/rtl/uart_tx.v

@@ -0,0 +1,103 @@
+`default_nettype none
+module uart_tx #(parameter CLOCKS_PER_BAUD=16'd868)(
+           input wire clk,
+           input wire rst_n,
+           input wire en_i,
+           input wire [7:0] data_i,
+           output reg tx_o,
+           output reg tx_done_o
+       );
+
+localparam s_idle = 5'b00001,
+           s_start = 5'b00010,
+           s_wr = 5'b00100,
+           s_stop = 5'b01000,
+           s_done = 5'b10000;
+
+reg en_cnt;
+reg [15:0] cnt;
+reg [4:0] state;
+reg [7:0] data_r;
+reg [2:0] tx_bits;
+
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+        cnt <= 16'd0;
+    else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
+        cnt <= 16'd0;
+    else
+        cnt <= cnt + 1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if (~rst_n) begin
+        state <= s_idle;
+        tx_o <= 1;
+        en_cnt <= 0;
+        data_r <= 0;
+        tx_bits <= 0;
+        tx_done_o <= 0;
+    end else begin
+        case (state)
+            s_idle: begin
+                data_r <= data_i;
+                tx_bits <= 0;
+                tx_done_o <= 0;
+                if (en_i == 1) begin
+                    en_cnt <= 1;
+                    state <= s_start;
+                end else begin
+                    en_cnt <= 0;
+                    state <= s_idle;
+                end
+            end
+
+            s_start: begin
+                if (cnt == CLOCKS_PER_BAUD)
+                    state <= s_wr;
+                else begin
+                    tx_o <= 0;
+                    state <= s_start;
+                end
+            end
+
+            s_wr: begin
+                if (cnt == CLOCKS_PER_BAUD) begin
+                    if (tx_bits == 3'd7)
+                        state <= s_stop;
+                    else begin
+                        tx_bits <= tx_bits + 1;
+                        state <= s_wr;
+                    end
+                end else begin
+                    tx_o <= data_r[tx_bits];
+                    state <= s_wr;
+                end
+            end
+
+            s_stop: begin
+                if (cnt == CLOCKS_PER_BAUD)
+                    state <= s_done;
+                else begin
+                    tx_o <= 1;
+                    state <= s_stop;
+                end
+            end
+
+            s_done: begin
+                en_cnt <= 0;
+                tx_done_o <= 1;
+                state <= s_idle;
+            end
+
+            default : begin
+                state <= s_idle;
+            end
+        endcase
+    end
+end
+
+endmodule
+    // Local Variables:
+    // verilog-library-directories:(".." "../rtl" ".")
+    // End:

uart/tb.v

@@ -0,0 +1 @@
+bench/uart_top_tb.v