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45f845f671
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can transmit data out, but in wrong order ...
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2020-11-01 09:30:46 -06:00 |
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aeaf18c2d4
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skip debounce in simulation
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2020-10-30 17:52:42 -05:00 |
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5a58da34af
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move debouncing parts to top module
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2020-10-27 07:50:25 -05:00 |
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92f059ab54
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use only top bits of the data to display
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2020-10-26 22:45:17 -05:00 |
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c6cc9bc99f
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change divison factor in clk_gen for 100 MHz
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2020-10-26 22:00:42 -05:00 |
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61bab9153d
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hack to use PLL in synthesizing, and fake 100 MHz on verilator
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2020-10-26 21:58:13 -05:00 |
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a0b211338c
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working stop watch
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2020-10-26 17:35:52 -05:00 |
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4886fad4b2
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tdc state machine
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2020-10-26 16:06:00 -05:00 |
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74dd3fb1d8
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resume with the TDC
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2020-10-25 22:49:43 -05:00 |
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7bb2d41932
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create a dummy clock gen, can include it in both sim and synth
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2020-10-22 21:58:42 -05:00 |
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1198429d53
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new project for tdc, copied code from blinky and changed structure
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2020-10-22 21:28:17 -05:00 |
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