74 lines
1.9 KiB
Verilog
74 lines
1.9 KiB
Verilog
`default_nettype none
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module top #(parameter WIDTH=24)(
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input wire i_clk,
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input wire i_startN,
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input wire i_stopN,
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input wire i_resetN,
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output wire o_ledN,
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output wire o_readyN,
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output wire [5:0] o_dataN,
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output wire o_led_row_0
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);
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wire clk_1Hz; // 1.4 Hz actually
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wire clk_100MHz;
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reg buf_led = 0;
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wire buf_ready;
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/* verilator lint_off UNUSED */
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parameter TDC_COUNTER_WIDTH = 28;
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wire [TDC_COUNTER_WIDTH-1:0] buf_data;
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assign o_readyN = ~buf_ready;
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assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
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/* verilator lint_on UNUSED */
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/* verilator lint_off PINMISSING */
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clk_gen #(.DIVISION(26)) clk_gen0 (
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.o_div_clk (clk_1Hz),
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.o_clk_100MHz (clk_100MHz),
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.i_clk (i_clk));
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/* verilator lint_on PINMISSING */
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reg db_start, db_stop;
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`ifdef VERILATOR
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always @(posedge clk_100MHz) begin
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db_start <= ~i_startN;
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db_stop <= ~i_stopN;
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end
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`else
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debounce db1 (
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// Outputs
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.db (db_start),
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// Inputs
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.clk (clk_100MHz),
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.reset (~i_resetN),
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.sw (~i_startN));
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debounce db2 (
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// Outputs
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.db (db_stop),
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// Inputs
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.clk (clk_100MHz),
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.reset (~i_resetN),
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.sw (~i_stopN));
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`endif
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tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
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// Outputs
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.o_ready (buf_ready),
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.o_data (buf_data),
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// Inputs
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.i_clk (clk_100MHz),
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.i_start (db_start),
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.i_stop (db_stop),
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.i_reset (~i_resetN));
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always @(posedge clk_1Hz) begin
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buf_led <= ~buf_led;
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end
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assign o_ledN = ~buf_led;
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assign o_led_row_0 = 1'b0;
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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