`default_nettype  none

module top #(parameter WIDTH=24)(
   input wire i_clk,
   input wire i_startN,
   input wire i_stopN,
   input wire i_resetN,
   output wire o_ledN,
   output wire o_readyN,
   output wire [5:0] o_dataN,
   output wire o_led_row_0
);
   wire clk_1Hz; // 1.4 Hz actually
   wire clk_100MHz;
   reg buf_led = 0;
   wire buf_ready;
   /* verilator lint_off UNUSED */
   parameter TDC_COUNTER_WIDTH = 28;
   wire [TDC_COUNTER_WIDTH-1:0] buf_data;
   assign o_readyN = ~buf_ready;
   assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
   /* verilator lint_on UNUSED */

   /* verilator lint_off PINMISSING */
   clk_gen #(.DIVISION(26)) clk_gen0 (
   .o_div_clk        (clk_1Hz),
   .o_clk_100MHz (clk_100MHz),
   .i_clk            (i_clk));
   /* verilator lint_on PINMISSING */
   reg db_start, db_stop;
`ifdef VERILATOR
   always @(posedge clk_100MHz) begin
      db_start <= ~i_startN;
      db_stop <= ~i_stopN;
   end
`else
   debounce db1 (
      // Outputs
      .db                       (db_start),
      // Inputs
      .clk                      (clk_100MHz),
      .reset                    (~i_resetN),
      .sw                       (~i_startN));
   debounce db2 (
      // Outputs
      .db                       (db_stop),
      // Inputs
      .clk                      (clk_100MHz),
      .reset                    (~i_resetN),
      .sw                       (~i_stopN));
`endif

   tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
   // Outputs
   .o_ready                    (buf_ready),
   .o_data                     (buf_data),
   // Inputs
   .i_clk                      (clk_100MHz),
   .i_start                    (db_start),
   .i_stop                     (db_stop),
   .i_reset                   (~i_resetN));

   always @(posedge clk_1Hz) begin
      buf_led <= ~buf_led;
   end

   assign o_ledN = ~buf_led;
   assign o_led_row_0 = 1'b0;
endmodule

// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: