46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
`default_nettype none
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module top #(parameter WIDTH=24)(
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input wire i_clk,
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output wire o_led,
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input wire i_start,
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input wire i_stop,
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input wire i_resetN,
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output wire o_ready,
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output wire [15:0] o_data,
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output wire o_led_row_0
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);
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wire clk_12MHz;
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reg buf_led = 0;
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clk_gen clk_gen_0 (/*autoinst*/
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// Outputs
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.o_clk (clk_12MHz),
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// Inputs
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.i_clk (i_clk));
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tdc tdc0(/*autoinst*/
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// Outputs
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.o_ready (o_ready),
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.o_data (o_data[15:0]),
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// Inputs
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.i_clk (clk_12MHz),
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.i_start (i_start),
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.i_stop (i_stop),
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.i_reset (~i_resetN));
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reg [WIDTH-1:0] counter;
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always @(posedge clk_12MHz) begin
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counter <= counter + 1'b1;
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buf_led <= counter[WIDTH-1];
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end
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assign o_led = ~buf_led;
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assign o_led_row_0 = 1'b0;
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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