uart tx using zipcpu tut5 code

2020-10-27 14:50:10 -05:00
parent 568775a169
commit ec6b3431be
8 changed files with 543 additions and 0 deletions
--- a/serialTx-tut5/constraints/timing.py
+++ b/serialTx-tut5/constraints/timing.py
@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)