From ec6b3431be19f0c3f52b48479082d4cffd424901 Mon Sep 17 00:00:00 2001 From: Nam Tran Date: Tue, 27 Oct 2020 14:50:10 -0500 Subject: [PATCH] uart tx using zipcpu tut5 code --- serialTx-tut5/Makefile | 72 ++++++++ serialTx-tut5/constraints/iceFUN.pcf | 8 + serialTx-tut5/constraints/timing.py | 1 + serialTx-tut5/rtl/clk_gen.v | 31 ++++ serialTx-tut5/rtl/pll_100MHz.v | 40 ++++ serialTx-tut5/rtl/top.v | 85 +++++++++ serialTx-tut5/rtl/txuart.v | 267 +++++++++++++++++++++++++++ serialTx-tut5/sim/top.cc | 39 ++++ 8 files changed, 543 insertions(+) create mode 100644 serialTx-tut5/Makefile create mode 100644 serialTx-tut5/constraints/iceFUN.pcf create mode 100644 serialTx-tut5/constraints/timing.py create mode 100644 serialTx-tut5/rtl/clk_gen.v create mode 100644 serialTx-tut5/rtl/pll_100MHz.v create mode 100644 serialTx-tut5/rtl/top.v create mode 100644 serialTx-tut5/rtl/txuart.v create mode 100644 serialTx-tut5/sim/top.cc diff --git a/serialTx-tut5/Makefile b/serialTx-tut5/Makefile new file mode 100644 index 0000000..46ac343 --- /dev/null +++ b/serialTx-tut5/Makefile @@ -0,0 +1,72 @@ +SIM_TARGET = build/top +BIN_TARGET = build/top.bin +PCF = constraints/iceFUN.pcf +TIMING = constraints/timing.py +YOSYS = yosys +PNR = nextpnr-ice40 +IPACK = icepack +BURN = iceFUNprog +SBY = sby + +VERILATOR=verilator +VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') +VINC := $(VERILATOR_ROOT)/include + +RTL_SRC := $(wildcard rtl/*.v) +SIM_SRC := $(wildcard sim/*.cc) +FV_SRC := sim/top.sby + +BUILD_DIR := ./build + +define colorecho + @tput setaf 6 + @echo $1 + @tput sgr0 +endef + +.PHONY: all burn fv clean sim +all: $(SIM_TARGET) $(BIN_TARGET) + +$(BUILD_DIR)/Vtop.cc: $(RTL_SRC) + $(call colorecho, "Running verilator") + mkdir -p $(BUILD_DIR) + $(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\ + --Mdir $(BUILD_DIR) --timescale-override 10ns/1ns + +$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc + make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk + +# std=c++11 flag is needed as of verilator v4.100 +$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a + $(call colorecho, "Compiling simulation executable") + g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\ + $(VINC)/verilated_vcd_c.cpp $^ -o $@ + echo "Run simulation with ./$(SIM_TARGET)" + +$(BUILD_DIR)/top.json: $(RTL_SRC) + $(call colorecho, "Synthesizing ...") + mkdir -p $(BUILD_DIR) + $(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^ + +$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING) + $(call colorecho, "Routing and building binary stream ...") + $(PNR) -r --hx8k --json $< --package cb132 \ + --asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \ + --pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q + $(IPACK) $(BUILD_DIR)/top.asc $@ + $(call colorecho, "Done!") + +sim: $(SIM_TARGET) + $(call colorecho, "Running simulation") + $(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd + +burn: $(BIN_TARGET) + $(BURN) $< + +fv: + $(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv + +clean: + rm -rf $(BUILD_DIR) + +$V.SILENT: diff --git a/serialTx-tut5/constraints/iceFUN.pcf b/serialTx-tut5/constraints/iceFUN.pcf new file mode 100644 index 0000000..8e35c8b --- /dev/null +++ b/serialTx-tut5/constraints/iceFUN.pcf @@ -0,0 +1,8 @@ +# For iceFUN board + +set_io --warn-no-port i_clk P7 +# set_io --warn-no-port i_start_tx C11 +# set_io --warn-no-port i_stopN A11 +# set_io --warn-no-port i_resetN C6 + +set_io --warn-no-port o_uart_tx A3 diff --git a/serialTx-tut5/constraints/timing.py b/serialTx-tut5/constraints/timing.py new file mode 100644 index 0000000..f949a2c --- /dev/null +++ b/serialTx-tut5/constraints/timing.py @@ -0,0 +1 @@ +ctx.addClock("i_clk", 100) diff --git a/serialTx-tut5/rtl/clk_gen.v b/serialTx-tut5/rtl/clk_gen.v new file mode 100644 index 0000000..f682aa6 --- /dev/null +++ b/serialTx-tut5/rtl/clk_gen.v @@ -0,0 +1,31 @@ +`default_nettype none +// dummy clock generator, should be replaced by a PLL clock gen eventually +module clk_gen #(parameter DIVISION=22)( + input wire i_clk, + output wire o_clk_100MHz, + output wire o_div_clk +); + +/* verilator lint_off PINCONNECTEMPTY */ +/* verilator lint_off PINMISSING */ +reg [DIVISION-1:0] counter = 0; +`ifdef VERILATOR + always @(posedge i_clk) begin + counter <= counter + 1; + end + + assign o_clk_100MHz = i_clk; +`else + pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked()); + always @(posedge o_clk_100MHz) begin + counter <= counter + 1; + end +`endif + +assign o_div_clk = counter[DIVISION-1]; +/* verilator lint_on PINCONNECTEMPTY */ +/* verilator lint_on PINMISSING */ +endmodule +// Local Variables: +// verilog-library-directories:(".." "./rtl" ".") +// End: diff --git a/serialTx-tut5/rtl/pll_100MHz.v b/serialTx-tut5/rtl/pll_100MHz.v new file mode 100644 index 0000000..30a7d3a --- /dev/null +++ b/serialTx-tut5/rtl/pll_100MHz.v @@ -0,0 +1,40 @@ +/** +* PLL configuration +* +* This Verilog module was generated automatically +* using the icepll tool from the IceStorm project. +* Use at your own risk. +* +* Given input frequency: 12.000 MHz +* Requested output frequency: 100.000 MHz +* Achieved output frequency: 100.500 MHz +*/ +// this module is skipped by verilator +`ifdef VERILATOR +`else + module pll_100MHz( + input i_clk, + output o_clk_100MHz, + output o_pll_locked + ); + + wire clk_int; + SB_PLL40_CORE #( + .FEEDBACK_PATH("SIMPLE"), + .DIVR(4'b0000), // DIVR = 0 + .DIVF(7'b1000010), // DIVF = 66 + .DIVQ(3'b011), // DIVQ = 3 + .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 + ) uut ( + .LOCK(o_pll_locked), + .RESETB(1'b1), + .BYPASS(1'b0), + .REFERENCECLK(i_clk), + .PLLOUTCORE(clk_int) + ); + + SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int), + .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz)); + +endmodule +`endif diff --git a/serialTx-tut5/rtl/top.v b/serialTx-tut5/rtl/top.v new file mode 100644 index 0000000..26c3f9a --- /dev/null +++ b/serialTx-tut5/rtl/top.v @@ -0,0 +1,85 @@ +`default_nettype none + +module top #(parameter WIDTH=24)( + input wire i_clk, + output wire o_uart_tx +); + parameter CLOCK_RATE_HZ = 100_000_000; // 100MHz clock + parameter BAUD_RATE = 115_200; // 115.2 KBaud + parameter INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE); + + wire clk_100MHz; + + /* verilator lint_off PINMISSING */ + clk_gen #(.DIVISION(26)) clk_gen0 (.o_clk_100MHz (clk_100MHz), .i_clk (i_clk)); + /* verilator lint_on PINMISSING */ + + reg tx_restart = 0; + reg [27:0] hz_counter; + + initial hz_counter = 28'h16; + always @(posedge clk_100MHz) begin + if (hz_counter == 0) + hz_counter <= CLOCK_RATE_HZ - 1'b1; + else + hz_counter <= hz_counter - 1'b1; + end + + always @(posedge clk_100MHz) + tx_restart <= (hz_counter == 1); + + wire tx_busy; + reg tx_stb; + reg [3:0] tx_index; + reg [7:0] tx_data; + + initial tx_index = 4'h0; + always @(posedge clk_100MHz) begin + if ((tx_stb)&&(!tx_busy)) + tx_index <= tx_index + 1'b1; + end + + always @(posedge clk_100MHz) begin + case(tx_index) + 4'h0: tx_data <= "H"; + 4'h1: tx_data <= "e"; + 4'h2: tx_data <= "l"; + 4'h3: tx_data <= "l"; + // + 4'h4: tx_data <= "o"; + 4'h5: tx_data <= ","; + 4'h6: tx_data <= " "; + 4'h7: tx_data <= "W"; + // + 4'h8: tx_data <= "o"; + 4'h9: tx_data <= "r"; + 4'ha: tx_data <= "l"; + 4'hb: tx_data <= "d"; + // + 4'hc: tx_data <= "!"; + 4'hd: tx_data <= " "; + 4'he: tx_data <= "\n"; + 4'hf: tx_data <= "\r"; + // + endcase + end + + // tx_stb is a request to send a character. + initial tx_stb = 1'b0; + always @(posedge clk_100MHz) begin + if (&tx_restart) + tx_stb <= 1'b1; + else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf)) + tx_stb <= 1'b0; + end + + // + // Instantiate a serial port module here + // + txuart #(INITIAL_UART_SETUP[23:0]) + transmitter(clk_100MHz, tx_stb, tx_data, o_uart_tx, tx_busy); +endmodule + +// Local Variables: +// verilog-library-directories:(".." "./rtl" ".") +// End: diff --git a/serialTx-tut5/rtl/txuart.v b/serialTx-tut5/rtl/txuart.v new file mode 100644 index 0000000..b74a59b --- /dev/null +++ b/serialTx-tut5/rtl/txuart.v @@ -0,0 +1,267 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: txuart.v +// +// Project: Verilog Tutorial Example file +// +// Purpose: Transmit outputs over a single UART line. This particular UART +// implementation has been extremely simplified: it does not handle +// generating break conditions, nor does it handle anything other than the +// 8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol. +// +// To interface with this module, connect it to your system clock, and +// pass it the byte of data you wish to transmit. Strobe the i_wr line +// high for one cycle, and your data will be off. Wait until the 'o_busy' +// line is low before strobing the i_wr line again--this implementation +// has NO BUFFER, so strobing i_wr while the core is busy will just +// get ignored. The output will be placed on the o_txuart output line. +// +// There are known deficiencies in the formal proof found within this +// module. These have been left behind for you (the student) to fix. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// +// Written and distributed by Gisselquist Technology, LLC +// +// This program is hereby granted to the public domain. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. +// +//////////////////////////////////////////////////////////////////////////////// +// +// +`default_nettype none +// +// +// +module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy); + parameter [23:0] CLOCKS_PER_BAUD = 24'd868; + input wire i_clk; + input wire i_wr; + input wire [7:0] i_data; + // And the UART output line itself + output wire o_uart_tx; + // A line to tell others when we are ready to accept data. If + // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte + // for transmission. + output reg o_busy; + + // Define several states + localparam [3:0] START = 4'h0, + BIT_ZERO = 4'h1, + BIT_ONE = 4'h2, + BIT_TWO = 4'h3, + BIT_THREE = 4'h4, + BIT_FOUR = 4'h5, + BIT_FIVE = 4'h6, + BIT_SIX = 4'h7, + BIT_SEVEN = 4'h8, + LAST = 4'h8, + IDLE = 4'hf; + + reg [23:0] counter; + reg [3:0] state; + reg [8:0] lcl_data; + reg baud_stb; + + // o_busy + // + // This is a register, designed to be true is we are ever busy above. + // originally, this was going to be true if we were ever not in the + // idle state. The logic has since become more complex, hence we have + // a register dedicated to this and just copy out that registers value. + + initial o_busy = 1'b0; + initial state = IDLE; + always @(posedge i_clk) + if ((i_wr)&&(!o_busy)) + // Immediately start us off with a start bit + { o_busy, state } <= { 1'b1, START }; + else if (baud_stb) + begin + if (state == IDLE) // Stay in IDLE + { o_busy, state } <= { 1'b0, IDLE }; + else if (state < LAST) begin + o_busy <= 1'b1; + state <= state + 1'b1; + end else // Wait for IDLE + { o_busy, state } <= { 1'b1, IDLE }; + end + + + + // lcl_data + // + // This is our working copy of the i_data register which we use + // when transmitting. It is only of interest during transmit, and is + // allowed to be whatever at any other time. Hence, if o_busy isn't + // true, we can always set it. On the one clock where o_busy isn't + // true and i_wr is, we set it and o_busy is true thereafter. + // Then, on any baud_stb (i.e. change between baud intervals) + // we simple logically shift the register right to grab the next bit. + initial lcl_data = 9'h1ff; + always @(posedge i_clk) + if ((i_wr)&&(!o_busy)) + lcl_data <= { i_data, 1'b0 }; + else if (baud_stb) + lcl_data <= { 1'b1, lcl_data[8:1] }; + + // o_uart_tx + // + // This is the final result/output desired of this core. It's all + // centered about o_uart_tx. This is what finally needs to follow + // the UART protocol. + // + assign o_uart_tx = lcl_data[0]; + + + // All of the above logic is driven by the baud counter. Bits must last + // CLOCKS_PER_BAUD in length, and this baud counter is what we use to + // make certain of that. + // + // The basic logic is this: at the beginning of a bit interval, start + // the baud counter and set it to count CLOCKS_PER_BAUD. When it gets + // to zero, restart it. + // + // However, comparing a 28'bit number to zero can be rather complex-- + // especially if we wish to do anything else on that same clock. For + // that reason, we create "baud_stb". baud_stb is + // nothing more than a flag that is true anytime baud_counter is zero. + // It's true when the logic (above) needs to step to the next bit. + // Simple enough? + // + // I wish we could stop there, but there are some other (ugly) + // conditions to deal with that offer exceptions to this basic logic. + // + // 1. When the user has commanded a BREAK across the line, we need to + // wait several baud intervals following the break before we start + // transmitting, to give any receiver a chance to recognize that we are + // out of the break condition, and to know that the next bit will be + // a stop bit. + // + // 2. A reset is similar to a break condition--on both we wait several + // baud intervals before allowing a start bit. + // + // 3. In the idle state, we stop our counter--so that upon a request + // to transmit when idle we can start transmitting immediately, rather + // than waiting for the end of the next (fictitious and arbitrary) baud + // interval. + // + // When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in + // the idle state, but we also just accepted a command to start writing + // the next word. At this point, the baud counter needs to be reset + // to the number of CLOCKS_PER_BAUD, and baud_stb set to zero. + // + // The logic is a bit twisted here, in that it will only check for the + // above condition when baud_stb is false--so as to make + // certain the STOP bit is complete. + initial baud_stb = 1'b1; + initial counter = 0; + always @(posedge i_clk) + if ((i_wr)&&(!o_busy)) + begin + counter <= CLOCKS_PER_BAUD - 1'b1; + baud_stb <= 1'b0; + end else if (!baud_stb) + begin + baud_stb <= (counter == 24'h01); + counter <= counter - 1'b1; + end else if (state != IDLE) + begin + counter <= CLOCKS_PER_BAUD - 1'b1; + baud_stb <= 1'b0; + end + +// +// +// FORMAL METHODS +// +// +// +`ifdef FORMAL + +`ifdef TXUART +`define ASSUME assume +`else +`define ASSUME assert +`endif + + // Setup + + reg f_past_valid; + + initial f_past_valid = 1'b0; + always @(posedge i_clk) + f_past_valid <= 1'b1; + + // Any outstanding request that was busy on the last cycle, + // should remain busy on this cycle + initial `ASSUME(!i_wr); + always @(posedge i_clk) + if ((f_past_valid)&&($past(i_wr))&&($past(o_busy))) + begin + `ASSUME(i_wr == $past(i_wr)); + `ASSUME(i_data == $past(i_data)); + end + + ////////////////////////////////// + // + // The contract + // + ////////////////////////////////// + + reg [7:0] fv_data; + always @(posedge i_clk) + if ((i_wr)&&(!o_busy)) + fv_data <= i_data; + + always @(posedge i_clk) + case(state) + IDLE: assert(o_uart_tx == 1'b1); + START: assert(o_uart_tx == 1'b0); + BIT_ZERO: assert(o_uart_tx == fv_data[0]); + BIT_ONE: assert(o_uart_tx == fv_data[1]); + BIT_TWO: assert(o_uart_tx == fv_data[2]); + BIT_THREE: assert(o_uart_tx == fv_data[3]); + BIT_FOUR: assert(o_uart_tx == fv_data[4]); + BIT_FIVE: assert(o_uart_tx == fv_data[5]); + BIT_SIX: assert(o_uart_tx == fv_data[6]); + BIT_SEVEN: assert(o_uart_tx == fv_data[7]); + default: assert(0); + endcase + + ////////////////////////////////// + // + // Internal state checks + // + ////////////////////////////////// + + + // + // Check the baud counter + // + + // The baud_stb needs to be identical to our counter being zero + always @(posedge i_clk) + assert(baud_stb == (counter == 0)); + + + always @(posedge i_clk) + if ((f_past_valid)&&($past(counter != 0))) + assert(counter == $past(counter - 1'b1)); + + always @(posedge i_clk) + assert(counter < CLOCKS_PER_BAUD); + + always @(posedge i_clk) + if (!baud_stb) + assert(o_busy); + +`endif // FORMAL +endmodule + diff --git a/serialTx-tut5/sim/top.cc b/serialTx-tut5/sim/top.cc new file mode 100644 index 0000000..42841e2 --- /dev/null +++ b/serialTx-tut5/sim/top.cc @@ -0,0 +1,39 @@ +#include +#include +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "Vtop.h" + +void tick(int tickcount, Vtop *tb, VerilatedVcdC* tfp) { + tb->eval(); + if (tfp) + tfp->dump(tickcount * 10 - 2); + tb->i_clk = 1; + tb->eval(); + if (tfp) + tfp->dump(tickcount * 10); + tb->i_clk = 0; + tb->eval(); + if (tfp) { + tfp->dump(tickcount * 10 + 5); + tfp->flush(); + } +} + +int main(int argc, char **argv) { + // Call commandArgs first! + Verilated::commandArgs(argc, argv); + + // Instantiate our design + Vtop *tb = new Vtop; + Verilated::traceEverOn(true); + VerilatedVcdC* tfp = new VerilatedVcdC; + + tb->trace(tfp, 00); + tfp->open("build/waveform.vcd"); + + unsigned tickcount = 0; + for (int k = 0; k < (1<<18); k++) + tick(++tickcount, tb, tfp); + +}