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uart tx using zipcpu tut5 code

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Nam Tran
2020-10-27 14:50:10 -05:00
parent 568775a169
commit ec6b3431be
8 changed files with 543 additions and 0 deletions
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85
serialTx-tut5/rtl/top.v Normal file
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`default_nettype none
module top #(parameter WIDTH=24)(
input wire i_clk,
output wire o_uart_tx
);
parameter CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
parameter BAUD_RATE = 115_200; // 115.2 KBaud
parameter INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
wire clk_100MHz;
/* verilator lint_off PINMISSING */
clk_gen #(.DIVISION(26)) clk_gen0 (.o_clk_100MHz (clk_100MHz), .i_clk (i_clk));
/* verilator lint_on PINMISSING */
reg tx_restart = 0;
reg [27:0] hz_counter;
initial hz_counter = 28'h16;
always @(posedge clk_100MHz) begin
if (hz_counter == 0)
hz_counter <= CLOCK_RATE_HZ - 1'b1;
else
hz_counter <= hz_counter - 1'b1;
end
always @(posedge clk_100MHz)
tx_restart <= (hz_counter == 1);
wire tx_busy;
reg tx_stb;
reg [3:0] tx_index;
reg [7:0] tx_data;
initial tx_index = 4'h0;
always @(posedge clk_100MHz) begin
if ((tx_stb)&&(!tx_busy))
tx_index <= tx_index + 1'b1;
end
always @(posedge clk_100MHz) begin
case(tx_index)
4'h0: tx_data <= "H";
4'h1: tx_data <= "e";
4'h2: tx_data <= "l";
4'h3: tx_data <= "l";
//
4'h4: tx_data <= "o";
4'h5: tx_data <= ",";
4'h6: tx_data <= " ";
4'h7: tx_data <= "W";
//
4'h8: tx_data <= "o";
4'h9: tx_data <= "r";
4'ha: tx_data <= "l";
4'hb: tx_data <= "d";
//
4'hc: tx_data <= "!";
4'hd: tx_data <= " ";
4'he: tx_data <= "\n";
4'hf: tx_data <= "\r";
//
endcase
end
// tx_stb is a request to send a character.
initial tx_stb = 1'b0;
always @(posedge clk_100MHz) begin
if (&tx_restart)
tx_stb <= 1'b1;
else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
tx_stb <= 1'b0;
end
//
// Instantiate a serial port module here
//
txuart #(INITIAL_UART_SETUP[23:0])
transmitter(clk_100MHz, tx_stb, tx_data, o_uart_tx, tx_busy);
endmodule
// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: