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skip debounce in simulation

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Nam Tran
2020-10-30 17:52:42 -05:00
parent ec6b3431be
commit aeaf18c2d4
2 changed files with 50 additions and 37 deletions
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64
tdc/rtl/top.v
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@@ -21,38 +21,44 @@ module top #(parameter WIDTH=24)(
assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
/* verilator lint_on UNUSED */
/* verilator lint_off PINMISSING */
/* verilator lint_off PINMISSING */
clk_gen #(.DIVISION(26)) clk_gen0 (
.o_div_clk (clk_1Hz),
.o_clk_100MHz (clk_100MHz),
.i_clk (i_clk));
/* verilator lint_on PINMISSING */
reg db_start, db_stop;
debounce db1 (
// Outputs
.db (db_start),
// Inputs
.clk (clk_100MHz),
.reset (~i_resetN),
.sw (~i_startN));
debounce db2 (
// Outputs
.db (db_stop),
// Inputs
.clk (clk_100MHz),
.reset (~i_resetN),
.sw (~i_stopN));
.o_div_clk (clk_1Hz),
.o_clk_100MHz (clk_100MHz),
.i_clk (i_clk));
/* verilator lint_on PINMISSING */
reg db_start, db_stop;
`ifdef VERILATOR
always @(posedge clk_100MHz) begin
db_start <= ~i_startN;
db_stop <= ~i_stopN;
end
`else
debounce db1 (
// Outputs
.db (db_start),
// Inputs
.clk (clk_100MHz),
.reset (~i_resetN),
.sw (~i_startN));
debounce db2 (
// Outputs
.db (db_stop),
// Inputs
.clk (clk_100MHz),
.reset (~i_resetN),
.sw (~i_stopN));
`endif
tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
// Outputs
.o_ready (buf_ready),
.o_data (buf_data),
// Inputs
.i_clk (clk_100MHz),
.i_start (db_start),
.i_stop (db_stop),
.i_reset (~i_resetN));
// Outputs
.o_ready (buf_ready),
.o_data (buf_data),
// Inputs
.i_clk (clk_100MHz),
.i_start (db_start),
.i_stop (db_stop),
.i_reset (~i_resetN));
always @(posedge clk_1Hz) begin
buf_led <= ~buf_led;