diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index edcb76f..177a7c3 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -21,38 +21,44 @@ module top #(parameter WIDTH=24)(
    assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
    /* verilator lint_on UNUSED */
 
-/* verilator lint_off PINMISSING */
+   /* verilator lint_off PINMISSING */
    clk_gen #(.DIVISION(26)) clk_gen0 (
-                      .o_div_clk        (clk_1Hz),
-                      .o_clk_100MHz (clk_100MHz),
-                      .i_clk            (i_clk));
-/* verilator lint_on PINMISSING */
-
-reg db_start, db_stop;
-debounce db1 (
-   // Outputs
-   .db                       (db_start),
-   // Inputs
-   .clk                      (clk_100MHz),
-   .reset                    (~i_resetN),
-   .sw                       (~i_startN));
-debounce db2 (
-   // Outputs
-   .db                       (db_stop),
-   // Inputs
-   .clk                      (clk_100MHz),
-   .reset                    (~i_resetN),
-   .sw                       (~i_stopN));
+   .o_div_clk        (clk_1Hz),
+   .o_clk_100MHz (clk_100MHz),
+   .i_clk            (i_clk));
+   /* verilator lint_on PINMISSING */
+   reg db_start, db_stop;
+`ifdef VERILATOR
+   always @(posedge clk_100MHz) begin
+      db_start <= ~i_startN;
+      db_stop <= ~i_stopN;
+   end
+`else
+   debounce db1 (
+      // Outputs
+      .db                       (db_start),
+      // Inputs
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_startN));
+   debounce db2 (
+      // Outputs
+      .db                       (db_stop),
+      // Inputs
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_stopN));
+`endif
 
    tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
-            // Outputs
-            .o_ready                    (buf_ready),
-            .o_data                     (buf_data),
-            // Inputs
-            .i_clk                      (clk_100MHz),
-            .i_start                    (db_start),
-            .i_stop                     (db_stop),
-            .i_reset                   (~i_resetN));
+   // Outputs
+   .o_ready                    (buf_ready),
+   .o_data                     (buf_data),
+   // Inputs
+   .i_clk                      (clk_100MHz),
+   .i_start                    (db_start),
+   .i_stop                     (db_stop),
+   .i_reset                   (~i_resetN));
 
    always @(posedge clk_1Hz) begin
       buf_led <= ~buf_led;
diff --git a/tdc/sim/top.cc b/tdc/sim/top.cc
index fca78c0..2d6178a 100644
--- a/tdc/sim/top.cc
+++ b/tdc/sim/top.cc
@@ -32,6 +32,7 @@ int main(int argc, char **argv) {
    tb->trace(tfp, 00);
    tfp->open("build/waveform.vcd");
 
+   // initial state
    tb->i_resetN = 1;
    tb->i_startN = 1;
    tb->i_stopN = 1;
@@ -39,6 +40,7 @@ int main(int argc, char **argv) {
    for (int k = 0; k < 2; k++) 
       tick(++tickcount, tb, tfp);
 
+   // reset pulse, then wait for a few clock cycles
    tb->i_resetN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_resetN = 1;
@@ -46,21 +48,26 @@ int main(int argc, char **argv) {
    for (int k = 0; k < 3; k++) 
       tick(++tickcount, tb, tfp);
 
-   for (int i = 0; i < 1000; i++) {
-      tb->i_startN = 0;
-      tick(++tickcount, tb, tfp);
-      tb->i_startN = 1;
-      tick(++tickcount, tb, tfp);
-   }
+   // relevant const
+   const unsigned int main_clk_Hz = 100 * 1000 * 1000; // 100 MHz
+   const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz
+   const unsigned int db_ticks = main_clk_Hz / db_clk_Hz;
 
-   for (int k = 0; k < 15; k++) 
+   // start pulse
+
+   tb->i_startN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_startN = 1;
+
+   for (int k = 0; k < 394; k++) 
       tick(++tickcount, tb, tfp);
 
+   // stop pulse
    tb->i_stopN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_stopN = 1;
 
-   for (int k = 0; k < 3; k++) 
+   for (int k = 0; k < 30; k++) 
       tick(++tickcount, tb, tfp);
 
    tb->i_resetN = 0;