create a dummy clock gen, can include it in both sim and synth

tdc/rtl/clk_gen.v

@@ -0,0 +1,13 @@
+`default_nettype none
+// dummy clock generator, should be replaced by a PLL clock gen eventually
+module clk_gen(
+   input wire i_clk,
+   output wire o_clk
+);
+
+assign o_clk = i_clk;
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

tdc/rtl/top.v

@@ -6,12 +6,23 @@ module top(i_clk, o_led, lcol1);
    output wire o_led;
    output wire lcol1;
 
+   wire clk_12MHz;
+
+   clk_gen clk_gen_0 (/*autoinst*/
+      // Outputs
+      .o_clk                 (clk_12MHz),
+      // Inputs
+      .i_clk                 (i_clk));
+
    reg [WIDTH-1:0] counter;
 
-   always @(posedge i_clk)
+   always @(posedge clk_12MHz)
       counter <= counter + 1'b1;
 
    assign o_led = counter[WIDTH-1];
    assign lcol1 = 1'b0;
 endmodule
 
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End: