Nam Tran 45f845f671 can transmit data out, but in wrong order ...

2020-11-01 09:30:46 -06:00

..

clk_gen.v

indent

2020-10-27 10:39:56 -05:00

debounce.v

add debouncing buttons before start/stop

2020-10-26 22:33:44 -05:00

pll_100MHz.v

hack to use PLL in synthesizing, and fake 100 MHz on verilator

2020-10-26 21:58:13 -05:00

pos_edge_detector.v

can transmit data out, but in wrong order ...

2020-11-01 09:30:46 -06:00

tdc.v

move debouncing parts to top module

2020-10-27 07:50:25 -05:00

top.v

can transmit data out, but in wrong order ...

2020-11-01 09:30:46 -06:00

txuart.v

can transmit data out, but in wrong order ...

2020-11-01 09:30:46 -06:00