18 lines
719 B
Verilog
18 lines
719 B
Verilog
`default_nettype none
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module pos_edge_detector (
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input wire i_sig, // Input signal for which positive edge has to be detected
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input wire i_clk, // Input signal for clock
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output wire o_pe); // Output signal that gives a pulse when a positive edge occurs
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reg sig_dly; // Internal signal to store the delayed version of signal
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// This always block ensures that sig_dly is exactly 1 clock behind sig
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always @ (posedge i_clk) begin
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sig_dly <= i_sig;
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end
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// Combinational logic where sig is AND with delayed, inverted version of sig
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// Assign statement assigns the evaluated expression in the RHS to the internal net pe
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assign o_pe = i_sig & ~sig_dly;
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endmodule
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