working stop watch

tdc/Makefile

@@ -1,10 +1,12 @@
 SIM_TARGET = build/top
 BIN_TARGET = build/top.bin
-PCF = iceFUN.pcf
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
 YOSYS = yosys
 PNR = nextpnr-ice40
 IPACK = icepack
 BURN = iceFUNprog
+SBY = sby
 
 VERILATOR=verilator
 VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
@@ -12,43 +14,59 @@ VINC := $(VERILATOR_ROOT)/include
 
 RTL_SRC := $(wildcard rtl/*.v)
 SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
 BUILD_DIR := ./build
 
-.PHONY: all burn
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all burn fv clean sim
 all: $(SIM_TARGET)  $(BIN_TARGET)
 
-# -GWIDTH=5 allows passing parameter to verilog module
 $(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
-	@echo "Running verilator"
-	@mkdir -p $(BUILD_DIR)
-	@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\
+	$(call colorecho, "Running verilator")
+	mkdir -p $(BUILD_DIR)
+	$(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\
 		--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
 
 $(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
-	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+	make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
 
 # std=c++11 flag is needed as of verilator v4.100
 $(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
-	@echo "Compiling simulation executable"
-	@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
+	$(call colorecho, "Compiling simulation executable")
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
 		$(VINC)/verilated_vcd_c.cpp $^ -o $@
-	@echo "Run simulation with ./$(SIM_TARGET)"
+	echo "Run simulation with ./$(SIM_TARGET)"
 
 $(BUILD_DIR)/top.json: $(RTL_SRC)
-	@echo "Synthesizing ..."
-	@mkdir -p $(BUILD_DIR)
-	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
 
-$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
-	@echo "Routing and building binary stream ..."
-	@$(PNR) -r --hx8k --json $< --package cb132 \
-		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) -q
-	@$(IPACK) $(BUILD_DIR)/top.asc $@
-	@echo "Done!"
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+sim: $(SIM_TARGET)
+	$(call colorecho, "Running simulation")
+	$(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd
 
 burn: $(BIN_TARGET)
-	@$(BURN) $<
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
 
-.PHONY: clean
 clean:
 	rm -rf $(BUILD_DIR)
+
+$V.SILENT:

tdc/constraints/iceFUN.pcf

@@ -0,0 +1,17 @@
+# For iceFUN board
+
+set_io --warn-no-port i_clk  	P7
+set_io --warn-no-port i_startN 	C11
+set_io --warn-no-port i_stopN 	A11
+set_io --warn-no-port i_resetN 	C6
+
+set_io --warn-no-port o_led_row_0	A12
+set_io --warn-no-port o_dataN[0] 	C10
+set_io --warn-no-port o_dataN[1] 	A10
+set_io --warn-no-port o_dataN[2] 	D7
+set_io --warn-no-port o_dataN[3] 	D6
+set_io --warn-no-port o_dataN[4] 	A7
+set_io --warn-no-port o_dataN[5] 	C7
+
+set_io --warn-no-port o_ledN 	A4
+set_io --warn-no-port o_readyN 	C4

tdc/constraints/timing.py

@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)

tdc/iceFUN.pcf

@@ -1,5 +0,0 @@
-# For iceFUN board
-
-set_io --warn-no-port o_led 	C10
-set_io --warn-no-port i_clk  	P7
-set_io --warn-no-port lcol1	A12

tdc/rtl/clk_gen.v

@@ -1,11 +1,17 @@
 `default_nettype none
 // dummy clock generator, should be replaced by a PLL clock gen eventually
-module clk_gen(
+module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
    output wire o_clk
 );
 
-assign o_clk = i_clk;
+reg [DIVISION-1:0] counter = 0;
+
+always @(posedge i_clk) begin
+   counter <= counter + 1;
+end
+
+assign o_clk = counter[DIVISION-1];
 
 endmodule
 // Local Variables:

tdc/rtl/tdc.v

@@ -0,0 +1,81 @@
+`default_nettype none
+
+module tdc #(parameter COUNTER_WIDTH=16)(
+   input wire i_clk,
+   input wire i_start,
+   input wire i_stop,
+   input wire i_reset,
+   output wire o_ready,
+   output wire [COUNTER_WIDTH-1:0] o_data
+);
+
+reg [COUNTER_WIDTH-1:0] counter;
+assign o_data = counter;
+
+// states
+localparam state_idle = 2'b00;
+localparam state_started = 2'b01;
+localparam state_running = 2'b10;
+localparam state_stopped = 2'b11;
+reg [1:0] current_state, next_state;
+
+// ensure that state changes each clock
+always @(posedge i_clk) begin
+   if (i_reset) begin
+      current_state <= state_idle;
+   end else begin
+      current_state <= next_state;
+   end
+end
+
+// state logic
+/* verilator lint_off COMBDLY */
+always @(*) begin
+   case (current_state)
+      state_idle: begin
+         if (i_start && (~i_stop))
+            next_state <= state_started;
+         else
+            next_state <= state_idle;
+      end
+      state_started: begin
+         if (~i_start && (~i_stop))
+            next_state <= state_running;
+         else
+            next_state <= state_started;
+      end
+      state_running: begin
+         if (~i_start && (i_stop))
+            next_state <= state_stopped;
+         else
+            next_state <= state_running;
+      end
+      state_stopped: begin
+         if (i_reset)
+            next_state <= state_idle;
+         else
+            next_state <= state_stopped;
+      end
+
+      default : next_state <= current_state;
+   endcase
+end
+/* verilator lint_on COMBDLY */
+
+// counter runs during running state only
+always @(posedge i_clk) begin
+   case (current_state)
+      state_idle: counter <= 0;
+      state_started: counter <= 0;
+      state_running: counter <= counter + 1;
+      state_stopped: counter <= counter;
+      default : counter <= 0;
+   endcase
+end
+
+assign o_ready = (current_state == state_stopped);
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

tdc/rtl/top.v

@@ -1,26 +1,44 @@
 `default_nettype  none
 
-module top(i_clk, o_led, lcol1);
-   parameter WIDTH = 24;
-   input wire i_clk;
-   output wire o_led;
-   output wire lcol1;
+module top #(parameter WIDTH=24)(
+   input wire i_clk,
+   input wire i_startN,
+   input wire i_stopN,
+   input wire i_resetN,
+   output wire o_ledN,
+   output wire o_readyN,
+   output wire [5:0] o_dataN,
+   output wire o_led_row_0
+);
+   wire clk_3Hz;
+   reg buf_led = 0;
+   wire buf_ready;
+   wire [5:0] buf_data;
+   assign o_readyN = ~buf_ready;
+   assign o_dataN = ~buf_data;
 
-   wire clk_12MHz;
+   clk_gen #(.DIVISION(22)) clk_gen0 (/*autoinst*/
+                      // Outputs
+                      .o_clk            (clk_3Hz),
+                      // Inputs
+                      .i_clk            (i_clk));
 
-   clk_gen clk_gen_0 (/*autoinst*/
-      // Outputs
-      .o_clk                 (clk_12MHz),
-      // Inputs
-      .i_clk                 (i_clk));
+   tdc #(.COUNTER_WIDTH(6)) tdc0 (/*autoinst*/
+            // Outputs
+            .o_ready                    (buf_ready),
+            .o_data                     (buf_data),
+            // Inputs
+            .i_clk                      (clk_3Hz),
+            .i_start                    (~i_startN),
+            .i_stop                     (~i_stopN),
+            .i_reset                   (~i_resetN));
 
-   reg [WIDTH-1:0] counter;
+   always @(posedge clk_3Hz) begin
+      buf_led <= ~buf_led;
+   end
 
-   always @(posedge clk_12MHz)
-      counter <= counter + 1'b1;
-
-   assign o_led = counter[WIDTH-1];
-   assign lcol1 = 1'b0;
+   assign o_ledN = ~buf_led;
+   assign o_led_row_0 = 1'b0;
 endmodule
 
 // Local Variables:

tdc/sim/top.cc

@@ -5,43 +5,65 @@
 #include "Vtop.h"
 
 void	tick(int tickcount, Vtop *tb, VerilatedVcdC* tfp) {
-	tb->eval();
-	if (tfp)
-		tfp->dump(tickcount * 10 - 2);
-	tb->i_clk = 1;
-	tb->eval();
-	if (tfp)
-		tfp->dump(tickcount * 10);
-	tb->i_clk = 0;
-	tb->eval();
-	if (tfp) {
-		tfp->dump(tickcount * 10 + 5);
-		tfp->flush();
-	}
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10 - 2);
+   tb->i_clk = 1;
+   tb->eval();
+   if (tfp)
+      tfp->dump(tickcount * 10);
+   tb->i_clk = 0;
+   tb->eval();
+   if (tfp) {
+      tfp->dump(tickcount * 10 + 5);
+      tfp->flush();
+   }
 }
 
 int main(int argc, char **argv) {
-	// Call commandArgs first!
-	Verilated::commandArgs(argc, argv);
+   // Call commandArgs first!
+   Verilated::commandArgs(argc, argv);
 
-	// Instantiate our design
-	Vtop *tb = new Vtop;
-	Verilated::traceEverOn(true);
-	VerilatedVcdC* tfp = new VerilatedVcdC;
+   // Instantiate our design
+   Vtop *tb = new Vtop;
+   Verilated::traceEverOn(true);
+   VerilatedVcdC* tfp = new VerilatedVcdC;
 
-	tb->trace(tfp, 00);
-	tfp->open("build/waveform.vcd");
+   tb->trace(tfp, 00);
+   tfp->open("build/waveform.vcd");
 
-	unsigned tickcount = 0;
-  int last_led = tb->o_led;
+   tb->i_resetN = 1;
+   tb->i_startN = 1;
+   tb->i_stopN = 1;
+   unsigned tickcount = 0;
+   for (int k = 0; k < 2; k++) 
+      tick(++tickcount, tb, tfp);
 
-	for(int k=0; k<(1 << 12); k++) {
-    tick(++tickcount, tb, tfp);
+   tb->i_resetN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_resetN = 1;
 
-    if (last_led != tb->o_led) {
-      printf("k = %7d, led = %d\n", k, tb->o_led);
-    }
+   for (int k = 0; k < 3; k++) 
+      tick(++tickcount, tb, tfp);
 
-    last_led = tb->o_led;
-	}
+   tb->i_startN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_startN = 1;
+
+   for (int k = 0; k < 15; k++) 
+      tick(++tickcount, tb, tfp);
+
+   tb->i_stopN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_stopN = 1;
+
+   for (int k = 0; k < 3; k++) 
+      tick(++tickcount, tb, tfp);
+
+   tb->i_resetN = 0;
+   tick(++tickcount, tb, tfp);
+   tb->i_resetN = 1;
+
+   for (int k = 0; k < 3; k++) 
+      tick(++tickcount, tb, tfp);
 }