20 lines
404 B
Verilog
20 lines
404 B
Verilog
`default_nettype none
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// dummy clock generator, should be replaced by a PLL clock gen eventually
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module clk_gen #(parameter DIVISION=22)(
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input wire i_clk,
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output wire o_clk
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);
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reg [DIVISION-1:0] counter = 0;
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always @(posedge i_clk) begin
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counter <= counter + 1;
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end
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assign o_clk = counter[DIVISION-1];
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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