blinky_with_pll, works on hardware but verilator does not know how to handle the SB40_PLL_CORE yet

This commit is contained in:
2020-10-19 22:25:27 -05:00
parent 08ff4b2dbb
commit ccdfe6da64
6 changed files with 156 additions and 0 deletions

48
blinky_with_pll/Makefile Normal file
View File

@@ -0,0 +1,48 @@
SIM_TARGET = build/blinky
BIN_TARGET = build/blinky.bin
PCF = iceFUN.pcf
YOSYS = yosys
PNR = nextpnr-ice40
IPACK = icepack
BURN = iceFUNprog
VERILATOR=verilator
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
VINC := $(VERILATOR_ROOT)/include
SOURCE = blinky.v pll_100MHz.v
.PHONY: all burn
all: $(SIM_TARGET) $(BIN_TARGET)
# -GWIDTH=5 allows passing parameter to verilog module
obj_dir/Vblinky.cpp: $(SOURCE)
@echo "Running verilator"
@$(VERILATOR) --trace -Wall -Wno-fatal -GWIDTH=10 -cc blinky.v pll_100MHz.v ../toolchain-verilator/build-data/share/SB_PLL40_CORE.v --top-module blinky
obj_dir/Vblinky__ALL.a: obj_dir/Vblinky.cpp
@make --no-print-directory -C obj_dir -f Vblinky.mk
# std=c++11 flag is needed from verilator v4.100
$(SIM_TARGET): blinky.cpp obj_dir/Vblinky__ALL.a
@echo "Compiling simulation executable"
@mkdir -p build
@g++ -I$(VINC) -I obj_dir -std=c++11 $(VINC)/verilated.cpp $(VINC)/verilated_vcd_c.cpp \
$^ -o $@
@echo "Run simulation with ./$(TARGET)"
$(BIN_TARGET): $(SOURCE)
@echo "Building binary stream"
@mkdir -p ./build
@$(YOSYS) -p "synth_ice40 -top blinky -json build/blinky.json" -q $^
@$(PNR) -r --hx8k --json build/blinky.json --package cb132 \
--asc build/blinky.asc --opt-timing --pcf $(PCF) -q
@$(IPACK) build/blinky.asc build/blinky.bin
burn: $(BIN_TARGET)
@$(BURN) $<
.PHONY: clean
clean:
rm -rf obj_dir/ build/