diff --git a/blinky_with_pll/.gitignore b/blinky_with_pll/.gitignore
new file mode 100644
index 0000000..7dd399a
--- /dev/null
+++ b/blinky_with_pll/.gitignore
@@ -0,0 +1 @@
+blinky
diff --git a/blinky_with_pll/Makefile b/blinky_with_pll/Makefile
new file mode 100644
index 0000000..a42e6ee
--- /dev/null
+++ b/blinky_with_pll/Makefile
@@ -0,0 +1,48 @@
+SIM_TARGET = build/blinky
+BIN_TARGET = build/blinky.bin
+PCF = iceFUN.pcf
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+
+SOURCE = blinky.v pll_100MHz.v
+
+.PHONY: all burn
+all: $(SIM_TARGET)  $(BIN_TARGET)
+
+# -GWIDTH=5 allows passing parameter to verilog module
+obj_dir/Vblinky.cpp: $(SOURCE)
+	@echo "Running verilator"
+	@$(VERILATOR) --trace -Wall -Wno-fatal -GWIDTH=10 -cc blinky.v pll_100MHz.v ../toolchain-verilator/build-data/share/SB_PLL40_CORE.v --top-module blinky 
+
+obj_dir/Vblinky__ALL.a: obj_dir/Vblinky.cpp
+	@make --no-print-directory -C obj_dir -f Vblinky.mk
+
+# std=c++11 flag is needed from verilator v4.100
+$(SIM_TARGET): blinky.cpp obj_dir/Vblinky__ALL.a
+	@echo "Compiling simulation executable"
+	@mkdir -p build
+	@g++ -I$(VINC) -I obj_dir -std=c++11 $(VINC)/verilated.cpp $(VINC)/verilated_vcd_c.cpp \
+		$^ -o $@
+	@echo "Run simulation with ./$(TARGET)"
+
+$(BIN_TARGET): $(SOURCE)
+	@echo "Building binary stream"
+	@mkdir -p ./build
+	@$(YOSYS) -p "synth_ice40 -top blinky -json build/blinky.json" -q $^
+	@$(PNR) -r --hx8k --json build/blinky.json --package cb132 \
+		--asc build/blinky.asc --opt-timing --pcf $(PCF) -q
+	@$(IPACK) build/blinky.asc build/blinky.bin
+
+burn: $(BIN_TARGET)
+	@$(BURN) $<
+
+.PHONY: clean
+clean:
+	rm -rf obj_dir/ build/
+
diff --git a/blinky_with_pll/blinky.cpp b/blinky_with_pll/blinky.cpp
new file mode 100644
index 0000000..43911ec
--- /dev/null
+++ b/blinky_with_pll/blinky.cpp
@@ -0,0 +1,47 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include "Vblinky.h"
+
+void	tick(int tickcount, Vblinky *tb, VerilatedVcdC* tfp) {
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10 - 2);
+	tb->sysclk = 1;
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10);
+	tb->sysclk = 0;
+	tb->eval();
+	if (tfp) {
+		tfp->dump(tickcount * 10 + 5);
+		tfp->flush();
+	}
+}
+
+int main(int argc, char **argv) {
+	// Call commandArgs first!
+	Verilated::commandArgs(argc, argv);
+
+	// Instantiate our design
+	Vblinky *tb = new Vblinky;
+	Verilated::traceEverOn(true);
+	VerilatedVcdC* tfp = new VerilatedVcdC;
+
+	tb->trace(tfp, 00);
+	tfp->open("build/waveform.vcd");
+
+	unsigned tickcount = 0;
+  int last_led = tb->o_led;
+
+	for(int k=0; k<(1 << 12); k++) {
+    tick(++tickcount, tb, tfp);
+
+    if (last_led != tb->o_led) {
+      printf("k = %7d, led = %d\n", k, tb->o_led);
+    }
+
+    last_led = tb->o_led;
+	}
+}
diff --git a/blinky_with_pll/blinky.v b/blinky_with_pll/blinky.v
new file mode 100644
index 0000000..adc674c
--- /dev/null
+++ b/blinky_with_pll/blinky.v
@@ -0,0 +1,22 @@
+`default_nettype  none
+
+module blinky(o_led, lcol1, sysclk);
+   parameter WIDTH = 24;
+   
+   output wire o_led;
+   output wire lcol1;
+   input wire sysclk;
+   wire clk_100MHz;
+   wire locked;
+
+   pll_100MHz pll_0 (.clock_in(sysclk), .clock_out(clk_100MHz), .locked(locked));
+
+   reg [WIDTH-1:0] counter;
+
+   always @(posedge clk_100MHz)
+      counter <= counter + 1'b1;
+
+   assign o_led = counter[WIDTH-1];
+   assign lcol1 = 1'b0;
+endmodule
+
diff --git a/blinky_with_pll/iceFUN.pcf b/blinky_with_pll/iceFUN.pcf
new file mode 100644
index 0000000..e74c6d0
--- /dev/null
+++ b/blinky_with_pll/iceFUN.pcf
@@ -0,0 +1,5 @@
+# For iceFUN board
+
+set_io --warn-no-port o_led C10
+set_io --warn-no-port sysclk P7
+set_io --warn-no-port lcol1	A12
diff --git a/blinky_with_pll/pll_100MHz.v b/blinky_with_pll/pll_100MHz.v
new file mode 100644
index 0000000..db44232
--- /dev/null
+++ b/blinky_with_pll/pll_100MHz.v
@@ -0,0 +1,33 @@
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:        12.000 MHz
+ * Requested output frequency:   50.000 MHz
+ * Achieved output frequency:    50.250 MHz
+ */
+
+module pll_100MHz(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),		// DIVR =  0
+		.DIVF(7'b1000010),	// DIVF = 66
+		.DIVQ(3'b100),		// DIVQ =  4
+		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule