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change divison factor in clk_gen for 100 MHz

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Nam Tran
2020-10-26 22:00:42 -05:00
parent 61bab9153d
commit c6cc9bc99f
1 changed files with 4 additions and 4 deletions
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8
tdc/rtl/top.v
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@@ -10,7 +10,7 @@ module top #(parameter WIDTH=24)(
output wire [5:0] o_dataN,
output wire o_led_row_0
);
wire clk_3Hz;
wire clk_1Hz; // 1.4 Hz actually
wire clk_100MHz;
reg buf_led = 0;
wire buf_ready;
@@ -19,8 +19,8 @@ module top #(parameter WIDTH=24)(
assign o_dataN = ~buf_data;
/* verilator lint_off PINMISSING */
clk_gen #(.DIVISION(22)) clk_gen0 (
.o_div_clk (clk_3Hz),
clk_gen #(.DIVISION(26)) clk_gen0 (
.o_div_clk (clk_1Hz),
.o_clk_100MHz (clk_100MHz),
.i_clk (i_clk));
/* verilator lint_on PINMISSING */
@@ -35,7 +35,7 @@ module top #(parameter WIDTH=24)(
.i_stop (~i_stopN),
.i_reset (~i_resetN));
always @(posedge clk_3Hz) begin
always @(posedge clk_1Hz) begin
buf_led <= ~buf_led;
end