From c6cc9bc99f09c88f086496b6126d10d211cfbd57 Mon Sep 17 00:00:00 2001 From: Nam Tran Date: Mon, 26 Oct 2020 22:00:42 -0500 Subject: [PATCH] change divison factor in clk_gen for 100 MHz --- tdc/rtl/top.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v index 2d9b5ca..cdf1a36 100644 --- a/tdc/rtl/top.v +++ b/tdc/rtl/top.v @@ -10,7 +10,7 @@ module top #(parameter WIDTH=24)( output wire [5:0] o_dataN, output wire o_led_row_0 ); - wire clk_3Hz; + wire clk_1Hz; // 1.4 Hz actually wire clk_100MHz; reg buf_led = 0; wire buf_ready; @@ -19,8 +19,8 @@ module top #(parameter WIDTH=24)( assign o_dataN = ~buf_data; /* verilator lint_off PINMISSING */ - clk_gen #(.DIVISION(22)) clk_gen0 ( - .o_div_clk (clk_3Hz), + clk_gen #(.DIVISION(26)) clk_gen0 ( + .o_div_clk (clk_1Hz), .o_clk_100MHz (clk_100MHz), .i_clk (i_clk)); /* verilator lint_on PINMISSING */ @@ -35,7 +35,7 @@ module top #(parameter WIDTH=24)( .i_stop (~i_stopN), .i_reset (~i_resetN)); - always @(posedge clk_3Hz) begin + always @(posedge clk_1Hz) begin buf_led <= ~buf_led; end