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resume with the TDC

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Nam Tran
2020-10-25 22:49:43 -05:00
parent 240b6e26d4
commit 74dd3fb1d8
5 changed files with 58 additions and 29 deletions
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60
tdc/Makefile
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@@ -1,10 +1,12 @@
SIM_TARGET = build/top SIM_TARGET = build/top
BIN_TARGET = build/top.bin BIN_TARGET = build/top.bin
PCF = iceFUN.pcf PCF = constraints/iceFUN.pcf
TIMING = constraints/timing.py
YOSYS = yosys YOSYS = yosys
PNR = nextpnr-ice40 PNR = nextpnr-ice40
IPACK = icepack IPACK = icepack
BURN = iceFUNprog BURN = iceFUNprog
SBY = sby
VERILATOR=verilator VERILATOR=verilator
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
@@ -12,43 +14,59 @@ VINC := $(VERILATOR_ROOT)/include
RTL_SRC := $(wildcard rtl/*.v) RTL_SRC := $(wildcard rtl/*.v)
SIM_SRC := $(wildcard sim/*.cc) SIM_SRC := $(wildcard sim/*.cc)
FV_SRC := sim/top.sby
BUILD_DIR := ./build BUILD_DIR := ./build
.PHONY: all burn define colorecho
@tput setaf 6
@echo $1
@tput sgr0
endef
.PHONY: all burn fv clean sim
all: $(SIM_TARGET) $(BIN_TARGET) all: $(SIM_TARGET) $(BIN_TARGET)
# -GWIDTH=5 allows passing parameter to verilog module
$(BUILD_DIR)/Vtop.cc: $(RTL_SRC) $(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
@echo "Running verilator" $(call colorecho, "Running verilator")
@mkdir -p $(BUILD_DIR) mkdir -p $(BUILD_DIR)
@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\ $(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\
--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns --Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc $(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
# std=c++11 flag is needed as of verilator v4.100 # std=c++11 flag is needed as of verilator v4.100
$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a $(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
@echo "Compiling simulation executable" $(call colorecho, "Compiling simulation executable")
@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\ g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
$(VINC)/verilated_vcd_c.cpp $^ -o $@ $(VINC)/verilated_vcd_c.cpp $^ -o $@
@echo "Run simulation with ./$(SIM_TARGET)" echo "Run simulation with ./$(SIM_TARGET)"
$(BUILD_DIR)/top.json: $(RTL_SRC) $(BUILD_DIR)/top.json: $(RTL_SRC)
@echo "Synthesizing ..." $(call colorecho, "Synthesizing ...")
@mkdir -p $(BUILD_DIR) mkdir -p $(BUILD_DIR)
@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^ $(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
@echo "Routing and building binary stream ..." $(call colorecho, "Routing and building binary stream ...")
@$(PNR) -r --hx8k --json $< --package cb132 \ $(PNR) -r --hx8k --json $< --package cb132 \
--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) -q --asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
@$(IPACK) $(BUILD_DIR)/top.asc $@ --pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q
@echo "Done!" $(IPACK) $(BUILD_DIR)/top.asc $@
$(call colorecho, "Done!")
sim: $(SIM_TARGET)
$(call colorecho, "Running simulation")
$(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd
burn: $(BIN_TARGET) burn: $(BIN_TARGET)
@$(BURN) $< $(BURN) $<
fv:
$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
.PHONY: clean
clean: clean:
rm -rf $(BUILD_DIR) rm -rf $(BUILD_DIR)
$V.SILENT:

15
tdc/constraints/iceFUN.pcf Normal file
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@@ -0,0 +1,15 @@
# For iceFUN board
set_io --warn-no-port i_clk P7
# set_io --warn-no-port i_request A5
set_io --warn-no-port o_led_row_0 A12
set_io --warn-no-port o_led C10
# set_io --warn-no-port o_led[0] C10
# set_io --warn-no-port o_led[1] A10
# set_io --warn-no-port o_led[2] D7
# set_io --warn-no-port o_led[3] D6
# set_io --warn-no-port o_led[4] A7
# set_io --warn-no-port o_led[5] C7
# set_io --warn-no-port o_led[6] A4
# set_io --warn-no-port o_busy C4

1
tdc/constraints/timing.py Normal file
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@@ -0,0 +1 @@
ctx.addClock("i_clk", 100)

5
tdc/iceFUN.pcf
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@@ -1,5 +0,0 @@
# For iceFUN board
set_io --warn-no-port o_led C10
set_io --warn-no-port i_clk P7
set_io --warn-no-port lcol1 A12

6
tdc/rtl/top.v
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@@ -1,10 +1,10 @@
`default_nettype none `default_nettype none
module top(i_clk, o_led, lcol1); module top(i_clk, o_led, o_led_row_0);
parameter WIDTH = 24; parameter WIDTH = 24;
input wire i_clk; input wire i_clk;
output wire o_led; output wire o_led;
output wire lcol1; output wire o_led_row_0;
wire clk_12MHz; wire clk_12MHz;
@@ -20,7 +20,7 @@ module top(i_clk, o_led, lcol1);
counter <= counter + 1'b1; counter <= counter + 1'b1;
assign o_led = counter[WIDTH-1]; assign o_led = counter[WIDTH-1];
assign lcol1 = 1'b0; assign o_led_row_0 = 1'b0;
endmodule endmodule
// Local Variables: // Local Variables: