From 74dd3fb1d86b5297feac2c48bd51b32b491d7f7f Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Sun, 25 Oct 2020 22:49:43 -0500
Subject: [PATCH] resume with the TDC

---
 tdc/Makefile               | 60 +++++++++++++++++++++++++-------------
 tdc/constraints/iceFUN.pcf | 15 ++++++++++
 tdc/constraints/timing.py  |  1 +
 tdc/iceFUN.pcf             |  5 ----
 tdc/rtl/top.v              |  6 ++--
 5 files changed, 58 insertions(+), 29 deletions(-)
 create mode 100644 tdc/constraints/iceFUN.pcf
 create mode 100644 tdc/constraints/timing.py
 delete mode 100644 tdc/iceFUN.pcf

diff --git a/tdc/Makefile b/tdc/Makefile
index 8b7629c..46ac343 100644
--- a/tdc/Makefile
+++ b/tdc/Makefile
@@ -1,10 +1,12 @@
 SIM_TARGET = build/top
 BIN_TARGET = build/top.bin
-PCF = iceFUN.pcf
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
 YOSYS = yosys
 PNR = nextpnr-ice40
 IPACK = icepack
 BURN = iceFUNprog
+SBY = sby
 
 VERILATOR=verilator
 VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
@@ -12,43 +14,59 @@ VINC := $(VERILATOR_ROOT)/include
 
 RTL_SRC := $(wildcard rtl/*.v)
 SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
 BUILD_DIR := ./build
 
-.PHONY: all burn
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all burn fv clean sim
 all: $(SIM_TARGET)  $(BIN_TARGET)
 
-# -GWIDTH=5 allows passing parameter to verilog module
 $(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
-	@echo "Running verilator"
-	@mkdir -p $(BUILD_DIR)
-	@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\
+	$(call colorecho, "Running verilator")
+	mkdir -p $(BUILD_DIR)
+	$(VERILATOR) --trace -Wall -cc $^ --top-module top -GWIDTH=10\
 		--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
 
 $(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
-	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+	make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
 
 # std=c++11 flag is needed as of verilator v4.100
 $(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
-	@echo "Compiling simulation executable"
-	@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
+	$(call colorecho, "Compiling simulation executable")
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
 		$(VINC)/verilated_vcd_c.cpp $^ -o $@
-	@echo "Run simulation with ./$(SIM_TARGET)"
+	echo "Run simulation with ./$(SIM_TARGET)"
 
 $(BUILD_DIR)/top.json: $(RTL_SRC)
-	@echo "Synthesizing ..."
-	@mkdir -p $(BUILD_DIR)
-	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
 
-$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
-	@echo "Routing and building binary stream ..."
-	@$(PNR) -r --hx8k --json $< --package cb132 \
-		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) -q
-	@$(IPACK) $(BUILD_DIR)/top.asc $@
-	@echo "Done!"
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+sim: $(SIM_TARGET)
+	$(call colorecho, "Running simulation")
+	$(SIM_TARGET) && open $(BUILD_DIR)/waveform.vcd
 
 burn: $(BIN_TARGET)
-	@$(BURN) $<
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
 
-.PHONY: clean
 clean:
 	rm -rf $(BUILD_DIR)
+
+$V.SILENT:
diff --git a/tdc/constraints/iceFUN.pcf b/tdc/constraints/iceFUN.pcf
new file mode 100644
index 0000000..1bf6912
--- /dev/null
+++ b/tdc/constraints/iceFUN.pcf
@@ -0,0 +1,15 @@
+# For iceFUN board
+
+set_io --warn-no-port i_clk  	P7
+# set_io --warn-no-port i_request 	A5
+
+set_io --warn-no-port o_led_row_0	A12
+set_io --warn-no-port o_led	C10
+# set_io --warn-no-port o_led[0] 	C10
+# set_io --warn-no-port o_led[1] 	A10
+# set_io --warn-no-port o_led[2] 	D7
+# set_io --warn-no-port o_led[3] 	D6
+# set_io --warn-no-port o_led[4] 	A7
+# set_io --warn-no-port o_led[5] 	C7
+# set_io --warn-no-port o_led[6] 	A4
+# set_io --warn-no-port o_busy 	C4
diff --git a/tdc/constraints/timing.py b/tdc/constraints/timing.py
new file mode 100644
index 0000000..f949a2c
--- /dev/null
+++ b/tdc/constraints/timing.py
@@ -0,0 +1 @@
+ctx.addClock("i_clk", 100)
diff --git a/tdc/iceFUN.pcf b/tdc/iceFUN.pcf
deleted file mode 100644
index c84781b..0000000
--- a/tdc/iceFUN.pcf
+++ /dev/null
@@ -1,5 +0,0 @@
-# For iceFUN board
-
-set_io --warn-no-port o_led 	C10
-set_io --warn-no-port i_clk  	P7
-set_io --warn-no-port lcol1	A12
diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index fbc8ad8..3f1c2be 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -1,10 +1,10 @@
 `default_nettype  none
 
-module top(i_clk, o_led, lcol1);
+module top(i_clk, o_led, o_led_row_0);
    parameter WIDTH = 24;
    input wire i_clk;
    output wire o_led;
-   output wire lcol1;
+   output wire o_led_row_0;
 
    wire clk_12MHz;
 
@@ -20,7 +20,7 @@ module top(i_clk, o_led, lcol1);
       counter <= counter + 1'b1;
 
    assign o_led = counter[WIDTH-1];
-   assign lcol1 = 1'b0;
+   assign o_led_row_0 = 1'b0;
 endmodule
 
 // Local Variables: