hack to use PLL in synthesizing, and fake 100 MHz on verilator

tdc/rtl/clk_gen.v

@@ -2,17 +2,29 @@
 // dummy clock generator, should be replaced by a PLL clock gen eventually
 module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
-   output wire o_clk
+   output wire o_clk_100MHz,
+   output wire o_div_clk
 );
 
+/* verilator lint_off PINCONNECTEMPTY */
+/* verilator lint_off PINMISSING */
    reg [DIVISION-1:0] counter = 0;
-
+`ifdef VERILATOR
    always @(posedge i_clk) begin
       counter <= counter + 1;
    end
 
-assign o_clk = counter[DIVISION-1];
+   assign o_clk_100MHz = i_clk;
+`else
+   pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
+   always @(posedge o_clk_100MHz) begin
+      counter <= counter + 1;
+   end
+`endif
 
+   assign o_div_clk = counter[DIVISION-1];
+/* verilator lint_on PINCONNECTEMPTY */
+/* verilator lint_on PINMISSING */
 endmodule
 // Local Variables:
 // verilog-library-directories:(".." "./rtl" ".")

tdc/rtl/pll_100MHz.v

@@ -0,0 +1,40 @@
+/**
+* PLL configuration
+*
+* This Verilog module was generated automatically
+* using the icepll tool from the IceStorm project.
+* Use at your own risk.
+*
+* Given input frequency:        12.000 MHz
+* Requested output frequency:  100.000 MHz
+* Achieved output frequency:   100.500 MHz
+*/
+// this module is skipped by verilator
+`ifdef VERILATOR
+`else
+   module pll_100MHz(
+      input  i_clk,
+      output o_clk_100MHz,
+      output o_pll_locked
+   );
+
+   wire clk_int;
+   SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),		// DIVR =  0
+      .DIVF(7'b1000010),	// DIVF = 66
+      .DIVQ(3'b011),		// DIVQ =  3
+      .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+   ) uut (
+      .LOCK(o_pll_locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(i_clk),
+      .PLLOUTCORE(clk_int)
+   );
+
+   SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
+      .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
+
+endmodule
+`endif

tdc/rtl/top.v

@@ -11,24 +11,26 @@ module top #(parameter WIDTH=24)(
    output wire o_led_row_0
 );
    wire clk_3Hz;
+   wire clk_100MHz;
    reg buf_led = 0;
    wire buf_ready;
    wire [5:0] buf_data;
    assign o_readyN = ~buf_ready;
    assign o_dataN = ~buf_data;
 
-   clk_gen #(.DIVISION(22)) clk_gen0 (/*autoinst*/
-                      // Outputs
-                      .o_clk            (clk_3Hz),
-                      // Inputs
+/* verilator lint_off PINMISSING */
+   clk_gen #(.DIVISION(22)) clk_gen0 (
+                      .o_div_clk        (clk_3Hz),
+                      .o_clk_100MHz (clk_100MHz),
                       .i_clk            (i_clk));
+/* verilator lint_on PINMISSING */
 
-   tdc #(.COUNTER_WIDTH(6)) tdc0 (/*autoinst*/
+   tdc #(.COUNTER_WIDTH(6)) tdc0 (
             // Outputs
             .o_ready                    (buf_ready),
             .o_data                     (buf_data),
             // Inputs
-            .i_clk                      (clk_3Hz),
+            .i_clk                      (clk_100MHz),
             .i_start                    (~i_startN),
             .i_stop                     (~i_stopN),
             .i_reset                   (~i_resetN));