32 lines
827 B
Verilog
32 lines
827 B
Verilog
`default_nettype none
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// dummy clock generator, should be replaced by a PLL clock gen eventually
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module clk_gen #(parameter DIVISION=22)(
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input wire i_clk,
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output wire o_clk_100MHz,
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output wire o_div_clk
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);
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/* verilator lint_off PINCONNECTEMPTY */
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/* verilator lint_off PINMISSING */
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reg [DIVISION-1:0] counter = 0;
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`ifdef VERILATOR
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always @(posedge i_clk) begin
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counter <= counter + 1;
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end
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assign o_clk_100MHz = i_clk;
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`else
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pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
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always @(posedge o_clk_100MHz) begin
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counter <= counter + 1;
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end
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`endif
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assign o_div_clk = counter[DIVISION-1];
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/* verilator lint_on PINCONNECTEMPTY */
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/* verilator lint_on PINMISSING */
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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