41 lines
949 B
Verilog
41 lines
949 B
Verilog
/**
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* PLL configuration
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*
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* This Verilog module was generated automatically
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* using the icepll tool from the IceStorm project.
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* Use at your own risk.
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*
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* Given input frequency: 12.000 MHz
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* Requested output frequency: 100.000 MHz
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* Achieved output frequency: 100.500 MHz
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*/
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// this module is skipped by verilator
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`ifdef VERILATOR
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`else
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module pll_100MHz(
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input i_clk,
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output o_clk_100MHz,
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output o_pll_locked
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);
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wire clk_int;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b1000010), // DIVF = 66
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.DIVQ(3'b011), // DIVQ = 3
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) uut (
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.LOCK(o_pll_locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(i_clk),
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.PLLOUTCORE(clk_int)
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);
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SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
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.GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
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endmodule
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`endif
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