use 1 Hz clock for visible walking

fsm-tut4/rtl/clk_gen.v

@@ -5,7 +5,25 @@ module clk_gen(
    output wire o_clk
 );
 
-assign o_clk = i_clk;
+// assign o_clk = i_clk;
+reg [31:0] counter;
+reg buf_clk;
+parameter CLK_RATE_HZ = 12_000_000;
+
+initial  begin
+   counter = 0;
+   buf_clk = 0;
+end
+assign o_clk = buf_clk;
+
+always @(posedge i_clk) begin
+   if (counter >= CLK_RATE_HZ/2 - 1) begin
+      counter <= 0;
+      buf_clk <= ~buf_clk; 
+   end
+   else
+      counter <= counter + 1;
+end
 
 endmodule
 // Local Variables: