From 3a9c0343c121b48517bc59fc3a50db4fef90cb9f Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Sun, 25 Oct 2020 21:38:28 -0500
Subject: [PATCH] use 1 Hz clock for visible walking

---
 fsm-tut4/rtl/clk_gen.v | 20 +++++++++++++++++++-
 fsm-tut4/rtl/top.v     | 12 ++++++------
 2 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/fsm-tut4/rtl/clk_gen.v b/fsm-tut4/rtl/clk_gen.v
index 491320f..53f2a7f 100644
--- a/fsm-tut4/rtl/clk_gen.v
+++ b/fsm-tut4/rtl/clk_gen.v
@@ -5,7 +5,25 @@ module clk_gen(
    output wire o_clk
 );
 
-assign o_clk = i_clk;
+// assign o_clk = i_clk;
+reg [31:0] counter;
+reg buf_clk;
+parameter CLK_RATE_HZ = 12_000_000;
+
+initial  begin
+   counter = 0;
+   buf_clk = 0;
+end
+assign o_clk = buf_clk;
+
+always @(posedge i_clk) begin
+   if (counter >= CLK_RATE_HZ/2 - 1) begin
+      counter <= 0;
+      buf_clk <= ~buf_clk; 
+   end
+   else
+      counter <= counter + 1;
+end
 
 endmodule
 // Local Variables:
diff --git a/fsm-tut4/rtl/top.v b/fsm-tut4/rtl/top.v
index 65432dc..d9746c7 100644
--- a/fsm-tut4/rtl/top.v
+++ b/fsm-tut4/rtl/top.v
@@ -8,11 +8,11 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
    input wire i_request;
    output wire o_busy;
 
-   wire clk_12MHz;
+   wire clk_1Hz;
 
    clk_gen clk_gen_0 (/*autoinst*/
       // Outputs
-      .o_clk                 (clk_12MHz),
+      .o_clk                 (clk_1Hz),
       // Inputs
       .i_clk                 (i_clk));
 
@@ -34,21 +34,21 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
       busy_buf = 0;
    end
 
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (!busy_buf && req_buf)
          busy_buf <= 1;
       else
          busy_buf <= (state != 4'h0);
    end
    // counter and strobe run only during busy signal is High
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (busy_buf)
          counter <= counter + 1'b1;
       else
          counter <= 0;
    end
 
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       if (!busy_buf && req_buf)
          state <= 4'h1;
       else if (state >= 4'hB)
@@ -58,7 +58,7 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
    end
 
    // fsm for led_buf
-   always @(posedge clk_12MHz) begin
+   always @(posedge clk_1Hz) begin
       case (state)
          4'h1: led_buf <= 6'b00_0001;
          4'h2: led_buf <= 6'b00_0010;