32 lines
589 B
Verilog
32 lines
589 B
Verilog
`default_nettype none
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// dummy clock generator, should be replaced by a PLL clock gen eventually
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module clk_gen(
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input wire i_clk,
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output wire o_clk
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);
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// assign o_clk = i_clk;
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reg [31:0] counter;
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reg buf_clk;
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parameter CLK_RATE_HZ = 12_000_000;
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initial begin
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counter = 0;
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buf_clk = 0;
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end
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assign o_clk = buf_clk;
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always @(posedge i_clk) begin
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if (counter >= CLK_RATE_HZ/2 - 1) begin
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counter <= 0;
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buf_clk <= ~buf_clk;
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end
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else
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counter <= counter + 1;
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end
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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