18 lines
312 B
Verilog
18 lines
312 B
Verilog
`default_nettype none
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module blinky(i_clk, o_led, lcol1);
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parameter WIDTH = 24;
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input wire i_clk;
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output wire o_led;
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output wire lcol1;
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reg [WIDTH-1:0] counter;
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always @(posedge i_clk)
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counter <= counter + 1'b1;
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assign o_led = counter[WIDTH-1];
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assign lcol1 = 1'b0;
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endmodule
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