Nam Tran c6cc9bc99f change divison factor in clk_gen for 100 MHz

2020-10-26 22:00:42 -05:00

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clk_gen.v

hack to use PLL in synthesizing, and fake 100 MHz on verilator

2020-10-26 21:58:13 -05:00

pll_100MHz.v

hack to use PLL in synthesizing, and fake 100 MHz on verilator

2020-10-26 21:58:13 -05:00

tdc.v

tdc state machine

2020-10-26 16:06:00 -05:00

top.v

change divison factor in clk_gen for 100 MHz

2020-10-26 22:00:42 -05:00